Patents by Inventor Shih-Yao Lin

Shih-Yao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for forming stacked layers and devices formed thereof
    Patent number: 11488858
    Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • MULTI-LAYER DIELECTRIC REFILL FOR PROFILE CONTROL IN SEMICONDUCTOR DEVICES
    Publication number: 20220344491
    Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.
    Type: Application
    Filed: April 22, 2021
    Publication date: October 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ya-Yi Tsai, Chi-Hsiang Chang, Shih-Yao LIN, Tzu-Chung Wang, Shu-Yuan Ku
  • Method of forming a semiconductor device by a replacement gate process
    Patent number: 11482421
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Method and system for fixing violation of layout
    Patent number: 11481536
    Abstract: A method includes the following operations: receiving design rule violations of a first layout; classifying, according to first chip features of the first layout, a first violation of the design rule violations into a first class of predefined classes; generating a first vector array for at least one of the first chip features of the first layout, that is associated with the first violation; selecting, according to the first vector array, first operations from pre-stored operations; generating a second layout based on the first layout and the first operations.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: October 25, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Yi-Lin Chuang, Song Liu, Pei-Pei Chen, Heng-Yi Lin, Shih-Yao Lin, Chin-Hsien Wang
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    Publication number: 20220336625
    Abstract: A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.
    Type: Application
    Filed: April 14, 2021
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Chao-Cheng Chen
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    Publication number: 20220336662
    Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.
    Type: Application
    Filed: April 14, 2021
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Li-Jung Kuo, Chen-Ping Chen, Ming-Ching Chang
  • Processes for removing spikes from gates
    Patent number: 11476347
    Abstract: A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Dummy Fin with Reduced Height and Method Forming Same
    Publication number: 20220328357
    Abstract: A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 13, 2022
    Inventors: Shih-Yao Lin, Te-Yung Liu, Chih-Han Lin
  • ETCH SELECTIVITY CONTROL FOR EPITAXY PROCESS WINDOW ENLARGEMENT IN SEMICONDUCTOR DEVICES
    Publication number: 20220328653
    Abstract: A semiconductor device and method for fabricating a semiconductor device includes etch selectivity tuning to enlarge epitaxy process windows. Through modification of etching processes and careful selection of materials, improvements in semiconductor device yield and performance can be delivered. Etch selectivity is controlled by using dilute gas, using assistive etch chemicals, controlling a magnitude of bias power used in the etching process, and controlling an amount of passivation gas used in the etching process, among other approaches. A recess is formed in a dummy fin in a region of the semiconductor where epitaxial growth occurs to further enlarge the epitaxy process window.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Shih-Yao Lin, Te-Yung Liu, Chih-Han Lin
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    Publication number: 20220310819
    Abstract: A semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. The semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. The semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. The semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. The semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. The air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.
    Type: Application
    Filed: October 4, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    Publication number: 20220302276
    Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    Publication number: 20220293594
    Abstract: A semiconductor device includes a dielectric fin between a first semiconductor channel and a second semiconductor channel. The semiconductor device includes a first gate structure. The first gate structure includes a first portion and a second portion separated from each other by the dielectric fin. The semiconductor device includes a first gate spacer that extends along sidewalls of the first portion of the first gate structure. The semiconductor device includes a second gate spacer that extends along sidewalls of the second portion of the first gate structure, respectively. At least one of the first gate spacer or second gate spacer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness, and wherein the first portion is closer to the dielectric fin than the second portion.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chieh-Ning Feng, Hsiao Wen Lee, Chao-Cheng Chen
  • Method for optimizing floor plan for an integrated circuit
    Patent number: 11443096
    Abstract: A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: September 13, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Yi-Lin Chuang, Shi-Wen Tan, Song Liu, Shih-Yao Lin, Wen-Yuan Fang
  • SpO2 miniprogram: AI SpO2 measurement app
    Patent number: 11432727
    Abstract: There is included an apparatus and system including video capture code configured to control a camera of a mobile phone to capture a video of at least a portion of skin, extraction code configured to extract at least one photoplethysmogram (PPG) signal from the video, determination code configured to determine a peripheral oxygen saturation (SpO2) value based on the PPG signal with respect to a blood flow at the portion of skin, and display code configured to control a display of the mobile phone to display the SpO2 value.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: September 6, 2022
    Assignee: TENCENT AMERICA LLC
    Inventors: Lianyi Han, Chao Huang, Xiaozhong Chen, Zhimin Huo, Shih-Yao Lin, Hui Tang, Tao Yang, Kun Wang, Wei Fan
  • Transistor gates and methods of forming thereof
    Patent number: 11437287
    Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Shu-Yuan Ku
  • USER DEVICE BASED PARKINSON'S DISEASE DETECTION
    Publication number: 20220257171
    Abstract: A method and user device for determining a unified Parkinson's disease rating scale (UPDRS) value associated with a user of the user device include obtaining video data associated with a movement of a body part of the user. The UPDRS value is determined using a model and the video data associated with the movement of the body part of the user. The UPDRS value is provided to permit an evaluation of the user based on the UPDRS value.
    Type: Application
    Filed: May 6, 2022
    Publication date: August 18, 2022
    Applicant: TENCENT AMERICA LLC
    Inventors: Lianyi HAN, Hui TANG, Yusheng XIE, Shih-Yao LIN, Qian ZHEN, Zhimin HUO, Wei FAN
  • PROGRAMMING SYSTEM FOR TIRE PRESSURE MONITORING SENSOR AND METHOD FOR PROGRAMMING
    Publication number: 20220253296
    Abstract: A programming system includes a programming tool and a tire pressure monitoring sensor. The programming tool automatically chooses proper programming steps according to the verification code to record programs into the compatible tire pressure monitoring sensors so as to improve the shortcoming of manual choosing and recording the correct brand programs.
    Type: Application
    Filed: January 17, 2022
    Publication date: August 11, 2022
    Inventors: SHIH-YAO LIN, CHIH-WEI YU
  • Dummy fin with reduced height and method forming same
    Patent number: 11410886
    Abstract: A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Yao Lin, Te-Yung Liu, Chih-Han Lin
  • PACKAGING METHOD FOR TIRE PRESSURE MONITORING SENSOR
    Publication number: 20220242177
    Abstract: A packaging method for a tire pressure monitoring sensor includes a step of placing, a step of pouring, and a step of hardening. In the step of placing, a sensing transmission module is put into a cavity of a modeling unit, and a positioning portion in the cavity restricts the sensing transmission module from moving transversely and toward an inner bottom of the cavity. In the step of pouring, a rubber compound is poured into the cavity and fills the cavity. The sensing transmission module is coated by the rubber compound to form a case on the outer surface of the sensing transmission module. In the step of hardening, the case is hardened and integrally formed with the sensing transmission module to form a tire pressure monitoring sensor which is removed from the cavity.
    Type: Application
    Filed: January 18, 2022
    Publication date: August 4, 2022
    Inventors: SHENG-HAO LEE, SHIH-YAO LIN
  • Fin Field-Effect Transistor Device and Method of Forming the Same
    Publication number: 20220238696
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen