Patents by Inventor Shih-Yin Hsiao
Shih-Yin Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10290718Abstract: A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320 nanometers, and the metal gate has at least one plug hole. The metal-oxide semiconductor transistor further includes at least one insulating plug disposed in the plug hole and two diffusion regions disposed respectively at two sides of the metal gate in the substrate.Type: GrantFiled: August 3, 2017Date of Patent: May 14, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Wen-Fang Lee, Nien-Chung Li, Chih-Chung Wang
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Publication number: 20190115260Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.Type: ApplicationFiled: November 15, 2017Publication date: April 18, 2019Applicant: United Microelectronics Corp.Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu
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Patent number: 10204996Abstract: A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.Type: GrantFiled: August 4, 2017Date of Patent: February 12, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Wen-Fang Lee, Nien-Chung Li, Chih-Chung Wang
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Publication number: 20190006528Abstract: A high voltage device includes a semiconductor substrate, an ion well, a Schottky diode in the ion well, an isolation structure in the ion well surrounding the Schottky diode, and an assistant gate surrounding the Schottky diode. The assistant gate is disposed only on the isolation structure and is not in direct contact with the ion well.Type: ApplicationFiled: July 27, 2017Publication date: January 3, 2019Inventors: Shih-Yin Hsiao, Kai-Kuen Chang, Ching-Chung Yang
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Patent number: 10147800Abstract: A method of fabricating a transistor with reduced hot carrier injection effects includes providing a substrate covered by a gate material layer. Later, the gate material layer is patterned into a gate electrode. Then, a mask layer is formed to cover part of the gate electrode and expose two ends of the gate electrode. Finally, a first implantation process is performed to implant dopants through the exposed two ends of the gate electrode into the substrate directly under the gate electrode to form two LDD regions by taking the mask layer as a mask.Type: GrantFiled: February 19, 2016Date of Patent: December 4, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuan-Liang Liu, Shih-Yin Hsiao, Ching-Chung Yang
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Publication number: 20180233556Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.Type: ApplicationFiled: April 12, 2018Publication date: August 16, 2018Applicant: United Microelectronics Corp.Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
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Publication number: 20180233416Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.Type: ApplicationFiled: April 16, 2018Publication date: August 16, 2018Inventors: Shih-Yin Hsiao, Kuan-Liang Liu
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Publication number: 20180197742Abstract: A doping method for a semiconductor device including the following steps is provided. A substrate is provided. The substrate has a channel region. The channel region includes a first edge region, a second edge region and a center region in a channel width direction substantially perpendicular to a channel length direction, and the center region is located between the first edge region and the second edge region. A first doping process is performed on the first edge region, the second edge region and the center region by using a first conductive type dopant. A second doping process is performed on the center region by using a second conductive type dopant.Type: ApplicationFiled: January 10, 2017Publication date: July 12, 2018Applicant: United Microelectronics Corp.Inventors: Kai-Kuen Chang, Shih-Yin Hsiao
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Patent number: 10020393Abstract: The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) transistor and a manufacturing method thereof. The LDMOS transistor includes a semiconductor substrate, an insulation structure, agate structure, and a plurality of floating electrodes. The insulation structure is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The floating electrodes are embedded in the insulation structure, wherein the floating electrode closest to the gate structure protrudes from a top surface of the insulation structure or the gate structure includes at least one branch portion embedded in the insulation structure, and the floating electrodes are separated from the gate structure.Type: GrantFiled: October 19, 2015Date of Patent: July 10, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Chia-Min Hung
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Patent number: 10008573Abstract: A high-voltage metal-oxide-semiconductor transistor device includes a semiconductor substrate, a gate structure, a first drift region, a first isolation structure, a drain region, and a first sub-gate structure. The gate structure and the first sub-gate structure are disposed on the semiconductor substrate and separated from each other. The first drift region is disposed in the semiconductor substrate and disposed at one side of the gate structure. The first isolation structure and the drain region are disposed in the first drift region and separated from each other. A part of the first drift region is disposed between the drain region and the first isolation structure. The first sub-gate structure is at least partially disposed on the first drift region disposed between the drain region and the first isolation structure, and the first sub-gate structure is electrically connected to the drain region.Type: GrantFiled: March 6, 2017Date of Patent: June 26, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Hsuan-Kai Chen, Tun-Jen Cheng
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Publication number: 20180158738Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.Type: ApplicationFiled: February 1, 2018Publication date: June 7, 2018Applicant: United Microelectronics Corp.Inventors: Kai-Kuen Chang, Shih-Yin Hsiao
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Patent number: 9985129Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.Type: GrantFiled: November 22, 2017Date of Patent: May 29, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
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Patent number: 9978647Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.Type: GrantFiled: December 28, 2015Date of Patent: May 22, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Kuan-Liang Liu
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Patent number: 9972678Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.Type: GrantFiled: October 6, 2016Date of Patent: May 15, 2018Assignee: United Microelectronics Corp.Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
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Publication number: 20180114842Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.Type: ApplicationFiled: November 15, 2016Publication date: April 26, 2018Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Ping-Hung Chiang
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Publication number: 20180108528Abstract: A method for forming a gate oxide layer on a substrate is provided, in which a region of the substrate is defined out by a shallow trench isolation (STI) structure. An oxide layer covers over the substrate and a mask layer with an opening to expose oxide layer corresponding to the region with an interface edge of the STI structure. The method includes forming a silicon spacer on a sidewall of the opening. A cleaning process is performed through the opening to expose the substrate at the region. An oxidation process is performed on the substrate at the region to form the gate oxide layer, wherein the silicon spacer is also oxidized to merge to an edge of the gate oxide layer.Type: ApplicationFiled: October 13, 2016Publication date: April 19, 2018Applicant: United Microelectronics Corp.Inventors: Shih-Yin Hsiao, Shu-Wen Lin, Ke-Feng Lin, Hsin-Liang Liu, Chang-Lin Chen
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Patent number: 9947746Abstract: A bipolar junction transistor (BJT) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in the semiconductor substrate. The second doping region is formed in the first doping region. The at least one stacked block is formed on and insulated from the second doping region. The third doping region is formed in the second doping region and disposed adjacent to the at least one stacked block. The conductive contact electrically connects the at least one stacked block with the third doping region.Type: GrantFiled: August 11, 2016Date of Patent: April 17, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Kai-Kuen Chang
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Publication number: 20180102408Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.Type: ApplicationFiled: October 6, 2016Publication date: April 12, 2018Applicant: United Microelectronics Corp.Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
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Publication number: 20180097104Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.Type: ApplicationFiled: November 22, 2017Publication date: April 5, 2018Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
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Patent number: 9929056Abstract: A method for forming gate structures for a HV device and a MV device is provided. The method includes forming a HV oxide layer on the substrate, covering a first region predetermined for forming the HV device. Further in the method, a dielectric mask is formed on a central portion of the HV oxide layer. A thermal oxidation process is performed to form a MV oxide layer on the substrate at a second region predetermined for forming the MV device, wherein peripheral portions of the HV oxide layer not covered by the dielectric mask grow thicker. The dielectric mask is removed. A conductive layer is formed over the substrate. The conductive layer, the HV oxide layer, the MV oxide layer are patterned to form the gate structures.Type: GrantFiled: November 22, 2016Date of Patent: March 27, 2018Assignee: United Microelectronics Corp.Inventors: Te-Chiu Tsai, Shih-Yin Hsiao, Ching-Wei Teng, Tun-Jen Cheng, Hung-Yi Tsai, Shan-Shi Huang