Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract: A mixed mode device. A polysilicon layer is over a substrate having a well therein. A first metal layer is formed over the polysilicon layer. A second metal layer is formed over the first metal layer. A conductive type of the well and a conductive type of the substrate are oppositive. A part of the polysilicon layer is positioned over the well. Heavily doped regions are further formed in the well beside the polysilicon layer. The polysilicon layer is used as gates of MOS transistors, and the heavily doped regions are used as source/drain regions of the MOS transistors. The first metal layer over the gate has a finger structure which electrically couples with the drain regions of the MOS transistors. The second metal layer electrically couples with the source regions through vias.