Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.

Abstract: A semiconductor device include a substrate, a first well region formed in the substrate, a first isolation structure formed in the first well region, a Schottky barrier structure formed on the first well region, and a plurality of assist structures formed on the first well region. The substrate includes a first conductivity type, the first well region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The assist structures physically contact the first well region.

Abstract: A semiconductor device include a substrate, a first well region formed in the substrate, a first isolation structure formed in the first well region, a Schottky barrier structure formed on the first well region, and a plurality of assist structures formed on the first well region. The substrate includes a first conductivity type, the first well region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The assist structures physically contact the first well region.

Abstract: A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate having a first region and a second region is provided, a shallow trench isolation (STI) is formed in the substrate to separate the first region and the second region, and a patterned hard mask is formed on the first region and part of the STI, in which the patterned hard mask exposes includes an opening to expose part of the STI. Next, a gas is driven-in through the exposed STI to alter an edge of the substrate on the first region.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.

Abstract: A method for fabricating isolation device is disclosed. The method includes the steps of: providing a substrate; forming a shallow trench isolation (STI) in the substrate, the STI includes a first STI and a second STI, and the first STI surrounds a first device region and the second STI surrounds a second device region; forming a first doped region between and contact the first STI and the second STI; and forming a first gate structure on the first doped region, the first STI and the second STI.

Abstract: A method of forming a semiconductor device is provided. At least two shallow trenches are formed in a substrate. An insulating layer is formed on surfaces of the substrate and the shallow trenches. A conductive layer is formed on the substrate between the shallow trenches. At least one spacer is formed on a sidewall of the conductive layer, wherein the spacer fills up each shallow trench.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

Abstract: A high voltage transistor includes a substrate, a well which is disposed within the substrate, a gate disposed on the well, a gate dielectric layer disposed between the well and the gate, two drift regions respectively disposed in the well at two sides of the gate, two source/drain regions respectively disposed within each drift region, wherein a width of the gate dielectric layer is smaller than a width of the source/drain region, and two isolation elements respectively disposed within each drift region

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a diffusion region, a first oxide layer, a second oxide layer and a polysilicon layer. The diffusion region is formed in the substrate and has a source and a drain extended along a first direction. The first oxide layer is formed on the substrate. The second oxide layer is formed in the substrate and adjacent to the drain. The polysilicon layer is formed on the substrate and has a first region, a second region, and a third region. The second region is formed on an edge of the second oxide layer and between the first region and the third region. A width of the second region is less than a width of the first region and a width of the third region along the first direction.

Abstract: A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.

Abstract: Provided is a semiconductor structure including a substrate, a first gate, a second gate, a third gate and an inter-gate dielectric layer. The substrate has a first area and a second area, and the first surface of the first area is lower than the second surface of the second area. The first gate is disposed on the first surface of the first area. The second gate includes metal and is disposed on the first gate. The inter-gate dielectric layer is disposed between the first and second gates. The third gate includes metal and is disposed on the second surface of the second area. A method of foaming a semiconductor structure is further provided.

Abstract: The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) transistor and a manufacturing method thereof. The LDMOS transistor includes a semiconductor substrate, an insulation structure, agate structure, and a plurality of floating electrodes. The insulation structure is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The floating electrodes are embedded in the insulation structure, wherein the floating electrode closest to the gate structure protrudes from a top surface of the insulation structure or the gate structure includes at least one branch portion embedded in the insulation structure, and the floating electrodes are separated from the gate structure.

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor transistor device and a manufacturing method thereof. First, a semiconductor substrate is provided and a dielectric layer and a conductive layer sequentially stacked on the semiconductor substrate. Then, the conductive layer is patterned to form a gate and a dummy gate disposed at a first side of the gate and followed by forming a first spacer between the gate and the dummy gate and a second spacer at a second side of the gate opposite to the first side, wherein the first spacer includes an indentation. Subsequently, the dummy gate is removed.

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. A method of forming a memory device is further provided.

Abstract: A transistor set forming process includes the following steps. A substrate having a first area and a second area is provided. An implantation process is performed to form a diffusion region of a first transistor in the substrate of the first area and a channel region of a second transistor in the substrate of the second area at the same time.

Abstract: Provided is a semiconductor device including a substrate, an insulating layer, a conductive layer and at least one spacer. The substrate has at least two shallow trenches therein. The conductive layer is disposed on the substrate between the shallow trenches. The insulating layer is disposed between the substrate and the conductive layer. The at least one spacer is disposed on one sidewall of the conductive layer and fills up each shallow trench. A method of forming a semiconductor device is further provided.

Abstract: A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.

Abstract: A method for fabricating isolation device is disclosed. The method includes the steps of: providing a substrate; forming a shallow trench isolation (STI) in the substrate, the STI includes a first STI and a second STI, and the first STI surrounds a first device region and the second STI surrounds a second device region; forming a first doped region between and contact the first STI and the second STI; and forming a first gate structure on the first doped region, the first STI and the second STI.