Patents by Inventor Shin-Hung Yeh
Shin-Hung Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087974Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Sheng Lin, Chin-Hua Wang, Shu-Shen Yeh, Chien-Hung Chen, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11929045Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.Type: GrantFiled: February 10, 2023Date of Patent: March 12, 2024Assignee: Apple Inc.Inventors: Shin-Hung Yeh, Abbas Jamshidi Roudbari, Ting-Kuo Chang
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Publication number: 20240061298Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.Type: ApplicationFiled: October 26, 2023Publication date: February 22, 2024Inventors: Shin-Hung Yeh, Warren S. Rieutort-Louis, Abbas Jamshidi Roudbari, Chien-Ya Lee, Lun Tsai
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Publication number: 20240065057Abstract: A display may include pixels arranged in rows and columns in an active area and display driver circuitry in an inactive area. Data lines for the pixels may be positioned in the active area. Fanout lines may be routed through the active area. Each fanout line may electrically connect the display driver circuitry to a respective data line. One or more pixels may include a drive transistor and a light-emitting diode that are connected in series between a first power supply terminal and a second power supply terminal. A conductive layer may form a first terminal (such as the source terminal, the gate terminal, or the drain terminal) for the drive transistor. A conductive shielding layer may be interposed between the conductive layer and a fanout line to mitigate capacitive coupling between the terminal of the drive transistor and the fanout line.Type: ApplicationFiled: June 2, 2023Publication date: February 22, 2024Inventors: Shin-Hung Yeh, Abbas Jamshidi Roudbari, Chien-Ya Lee, I-Cheng Shih, Shyuan Yang, Tsung-Ting Tsai
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Patent number: 11852938Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.Type: GrantFiled: December 2, 2022Date of Patent: December 26, 2023Assignee: Apple Inc.Inventors: Shin-Hung Yeh, Warren S Rieutort-Louis, Abbas Jamshidi Roudbari, Chien-Ya Lee, Lun Tsai
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Patent number: 11818912Abstract: A display may have organic light-emitting diode pixels formed from thin-film circuitry. The thin-film circuitry may be formed in thin-film transistor (TFT) layers and the organic light-emitting diodes may include anodes and cathodes and an organic emissive layer formed over the TFT layers between the anodes and cathodes. The organic emissive layer may be formed via chemical evaporation techniques. The display may include moisture blocking structures such as organic emissive layer disconnecting structures that introduce one or more gaps in the organic emissive layer during evaporation so that any potential moisture permeating path from the display panel edge to the active area of the display is completely terminated.Type: GrantFiled: October 31, 2019Date of Patent: November 14, 2023Assignee: Apple Inc.Inventors: Tsung-Ting Tsai, Abbas Jamshidi Roudbari, Chuan-Sheng Wei, HanChi Ting, Jae Won Choi, Jianhong Lin, Nai-Chih Kao, Shih Chang Chang, Shin-Hung Yeh, Takahide Ishii, Ting-Kuo Chang, Yu Hung Chen, Yu-Wen Liu, Yu-Chuan Pai, Andrew Lin
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Patent number: 11741904Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.Type: GrantFiled: March 19, 2021Date of Patent: August 29, 2023Assignee: Apple Inc.Inventors: Ting-Kuo Chang, Abbas Jamshidi Roudbari, Tsung-Ting Tsai, Warren S. Rieutort-Louis, Shinya Ono, Shin-Hung Yeh, Chien-Ya Lee, Shyuan Yang
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Publication number: 20230221606Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.Type: ApplicationFiled: March 10, 2023Publication date: July 13, 2023Inventors: Shin-Hung Yeh, Warren S. Rieutort-Louis, Abbas Jamshidi Roudbari, Chien-Ya Lee, Lun Tsai
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Publication number: 20230197028Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.Type: ApplicationFiled: February 10, 2023Publication date: June 22, 2023Inventors: Shin-Hung Yeh, Abbas Jamshidi Roudbari, Ting-Kuo Chang
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Patent number: 11619851Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.Type: GrantFiled: November 12, 2021Date of Patent: April 4, 2023Assignee: Apple Inc.Inventors: Shin-Hung Yeh, Warren S. Rieutort-Louis, Abbas Jamshidi Roudbari, Chien-Ya Lee, Lun Tsai
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Publication number: 20230089447Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.Type: ApplicationFiled: December 2, 2022Publication date: March 23, 2023Inventors: Shin-Hung Yeh, Warren S. Rieutort-Louis, Abbas Jamshidi Roudbari, Chien-Ya Lee, Lun Tsai
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Patent number: 11594190Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.Type: GrantFiled: August 12, 2021Date of Patent: February 28, 2023Assignee: Apple Inc.Inventors: Shin-Hung Yeh, Abbas Jamshidi Roudbar, Ting-Kuo Chang
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Patent number: 11579503Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.Type: GrantFiled: November 12, 2021Date of Patent: February 14, 2023Assignee: Apple Inc.Inventors: Shin-Hung Yeh, Warren S. Rieutort-Louis, Abbas Jamshidi Roudbari, Chien-Ya Lee, Lun Tsai
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Publication number: 20220165814Abstract: An electronic device may include a display and a sensor under the display. The display may include an array of subpixels for displaying an image to a user of the electronic device. At least a portion of the array of subpixels may be selectively removed in a pixel removal region to improve optical transmittance to the sensor through the display. The pixel removal region may include a plurality of pixel free regions that are devoid of thin-film transistor structures, that are devoid of power supply lines, that have continuous open areas due to rerouted row/column lines, that are partially devoid of touch circuitry, that optionally include dummy contacts, and/or have selectively patterned display layers.Type: ApplicationFiled: April 8, 2020Publication date: May 26, 2022Inventors: Warren S. Rieutort-Louis, Woo Shik Jung, Abbas Jamshidi Roudbari, Shin-Hung Yeh, Christopher E. Glazowski, Jean-Pierre S. Guillou, Yuchi Che
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Publication number: 20220066272Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.Type: ApplicationFiled: November 12, 2021Publication date: March 3, 2022Inventors: Shin-Hung Yeh, Warren S. Rieutort-Louis, Abbas Jamshidi Roudbari, Chien-Ya Lee, Lun Tsai
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Patent number: 11204534Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.Type: GrantFiled: October 28, 2020Date of Patent: December 21, 2021Assignee: Apple Inc.Inventors: Shin-Hung Yeh, Warren S. Rieutort-Louis, Abbas Jamshidi Roudbari, Chien-Ya Lee, Lun Tsai
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Publication number: 20210375225Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Inventors: Shin-Hung Yeh, Abbas Jamshidi Roudbari, Ting-Kuo Chang
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Patent number: 11100877Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.Type: GrantFiled: July 22, 2019Date of Patent: August 24, 2021Assignee: Apple Inc.Inventors: Shin-Hung Yeh, Abbas Jamshidi Roudbari, Ting-Kuo Chang
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Publication number: 20210210022Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.Type: ApplicationFiled: March 19, 2021Publication date: July 8, 2021Inventors: Ting-Kuo Chang, Abbas Jamshidi Roudbari, Tsung-Ting Tsai, Warren S. Rieutort-Louis, Shinya Ono, Shin-Hung Yeh, Chien-Ya Lee, Shyuan Yang
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Patent number: 10984727Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.Type: GrantFiled: August 31, 2018Date of Patent: April 20, 2021Assignee: Apple Inc.Inventors: Ting-Kuo Chang, Abbas Jamshidi Roudbari, Tsung-Ting Tsai, Warren S. Rieutort-Louis, Shinya Ono, Shin-Hung Yeh, Chien-Ya Lee, Shyuan Yang