Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be scanned in each frame. In the partial scanning mode, only a subset of the rows of the display may be scanned in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. The gate driver circuitry may include a shift register that includes a plurality of register circuits. At least one register circuit may have a first input and a second input that is different than the first input.

Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be enabled to emit light in each frame. In the partial scanning mode, only a subset of the rows of the display may be enabled to emit light in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. To ensure uniform transistor stress across the display, the scanning driver for the display may scan the disabled rows in the partial scanning mode even though the rows will not be used to emit light.

Abstract: A display may have an array of pixels. A transparent conductive layer may serve as a common voltage electrode layer and may distribute a common voltage to each of the pixels. Metal layers may be used to form routing structures. One of the metal layers may be patterned to form gate lines that distribute control signals to thin-film transistors in the pixels. Touch sensor circuitry may be coupled to horizontal and vertical capacitive touch sensor electrodes formed from the transparent conductive layer. A touch sensor signal border routing path in an inactive area of the display may have openings that run parallel to the gate lines and that each overlap one of the gate lines to reduce capacitive coupling between the gate lines and the touch sensor signal border routing path.

Abstract: A display may have an array of pixels that forms an active display area for displaying images. An inactive border area of the display may have contact pads to which integrated circuits and flexible printed circuits may be attached. The contact pads may be free of organic planarization layers and may be formed from multiple stacked conductive layers. The inactive portion of the display may include electrostatic discharge protection structures associated with the pads, metal layers that form signal paths extending between the pads and the pixels, interlayer dielectric layers for protecting the metal layers that form the signal paths, polysilicon footer structures that help prevent undercutting of gate insulator material in the vicinity of the pads, and other pad and signal line structures.

Abstract: A gate drive circuit may include a latch circuit, a first transmission gate, and a second transmission gate. The first transmission gate and the second transmission gate may both be directly coupled to the latch circuit and may be directly coupled to a first gate line and a second gate line, respectively. The latch circuit may receive an electrical signal from a third gate line adjacent to the second gate line, such that the electrical signal is configured to reset a state of the latch circuit.

Abstract: Improvement of visual uniformity of an integrated touch screen display is provided. A touch screen can include common electrodes separated by gaps in a Vcom layer. To improve visual non-uniformity in the display resulting from the gaps, a first set of semi-transparent dummy features (primary-dummy features) can be formed on a second layer at the locations of the gaps, and a second set of dummy features (supplementary-dummy features) can also be formed on the second layer or another layer to mitigate low spatial resolution of the primary-dummy features and/or non-uniform spacing of the primary-dummy features. In some examples, holes or slits can be formed in the Vcom layer at areas of the supplementary-dummy features to further improve visual uniformity.

Abstract: A gate drive circuit may include a latch circuit, a first transmission gate, and a second transmission gate. The first transmission gate and the second transmission gate may both be directly coupled to the latch circuit and may be directly coupled to a first gate line and a second gate line, respectively. The latch circuit may receive an electrical signal from a third gate line adjacent to the second gate line, such that the electrical signal is configured to reset a state of the latch circuit.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer disposed between the first substrate and the second substrate, a common electrode layer disposed on the first substrate and a plurality of pixel structures disposed on the second substrate. Each of the pixel structure includes a first data line, a second data line, a third data line and at least a capacitance adjusting layer. The capacitance adjusting layer is disposed between the common electrode layer and the second data line.

Abstract: A pixel structure includes a plurality of data lines and a common line. The common line overlaps each data line, and is coupled with each data line to respectively form a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, a fourth coupling capacitor, a fifth coupling capacitor, and a sixth coupling capacitor. The third coupling capacitor is smaller than the second coupling capacitor, and the fifth coupling capacitor is smaller than the fourth coupling capacitor.

Abstract: A pixel structure includes at least one first sub-pixel electrode, at least one second sub-pixel electrode, at least one common line, at least one first transistor electrically connected to the first sub-pixel electrode, and at least one second transistor electrically connected to the second sub-pixel electrode. The common line overlaps and is coupled respectively with the first sub-pixel electrode and the second sub-pixel electrode so as to respectively form a first storage capacitor and a second storage capacitor. The second storage capacitor is larger than the first storage capacitor. A first adjusting capacitor of the first transistor is larger than a second adjusting capacitor of the second transistor.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer disposed between the first substrate and the second substrate, a common electrode layer disposed on the first substrate and a plurality of pixel structures disposed on the second substrate. Each of the pixel structure includes a first data line, a second data line, a third data line and at least a capacitance adjusting layer. The capacitance adjusting layer is disposed between the common electrode layer and the second data line.

Abstract: A pixel structure includes a plurality of data lines and a common line. The common line overlaps each data line, and is coupled with each data line to respectively form a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, a fourth coupling capacitor, a fifth coupling capacitor, and a sixth coupling capacitor. The third coupling capacitor is smaller than the second coupling capacitor, and the fifth coupling capacitor is smaller than the fourth coupling capacitor.

Abstract: A pixel structure includes at least one first sub-pixel electrode, at least one second sub-pixel electrode, at least one common line, at least one first transistor electrically connected to the first sub-pixel electrode, and at least one second transistor electrically connected to the second sub-pixel electrode. The common line overlaps and is coupled respectively with the first sub-pixel electrode and the second sub-pixel electrode so as to respectively form a first storage capacitor and a second storage capacitor. The second storage capacitor is larger than the first storage capacitor. A first adjusting capacitor of the first transistor is larger than a second adjusting capacitor of the second transistor.

Abstract: A liquid crystal display panel includes an active device substrate, an opposite substrate and a liquid crystal layer. The active device substrate includes a plurality of scan lines, a plurality of data lines intersected with the scan lines, and a plurality of pixels. Each pixel at least includes a first, second, and third sub-pixel. The first, second, and third sub-pixels in each pixel are electrically connected with different data lines respectively, while being electrically connected with the same scan line. The opposite substrate having a common electrode is disposed above the active device substrate. Coupling capacitance (Cdc1) between the data line connected with the second sub-pixel and the common electrode is substantially greater than coupling capacitance (Cdc2) between the data line connected with the first sub-pixel and/or third sub-pixel and the common electrode. The liquid crystal layer is disposed between the active device substrate and the opposite substrate.

Abstract: A DC-DC converter for a display. The DC-DC converter comprises a negative voltage generator, a level sifter and a DC-DC sub-converter. The negative generator generates a negative voltage. The level shifter, coupled to the negative voltage generator, generates complementary switch control signals. The DC-DC sub-converter coupled to the level shifter operates in response to the complementary switch control signals.

Abstract: A data driving circuit and organic light emitting diode display, comprising a D/A converter, a switch unit, a first analog sampling storage circuit and a second analog sampling storage circuit. The first analog sampling storage circuit is controlled by a first signal for storing corresponding first analog transformed data in the first cycle, and controlled by a second signal for outputting first analog data corresponding to the first analog transformed data in the second cycle. The second analog sampling storage circuit is controlled by the second signal for storing the second analog transformed data in the second cycle, and controlled by the first signal for outputting second analog data corresponding to the second analog transformed data in a third cycle.

Abstract: A compensating circuit for calibrating reference voltage, which is coupled to an operation amplifier having an input end and an output end within a reference voltage driving circuit, is provided in the present invention. The compensating circuit comprises a first capacitor, a second capacitor, and a first switch. The first capacitor is utilized for storing the potential with respect to the reference voltage. The second capacitor is coupled to the operation amplifier for storing the potential difference between the input end and the output end of the operation amplifier. The first switch is electrically connecting to the first capacitor and the second capacitor. When turning on the first switch, the potentials stored in the first capacitor and the second capacitor are combined and input to the operation amplifier to have an output voltage level substantially identical to the reference voltage.

Abstract: An exemplary a liquid crystal display includes a plurality of scanning lines and control lines, a plurality of first pixel units and second pixel units, and a data line driving chip. The first and second pixel units are connected to be under control of the scanning lines and the control lines. The data line driving chip includes a plurality of output terminals. During a period when one of the scanning lines is scanned, the corresponding first and second pixel units are able to receive a first gradation voltage signal output from the output terminals, and subsequently only the corresponding second pixel units are able to receive a second gradation voltage signal output from the output terminals. A method of driving such kind of liquid crystal display is also provided.

Abstract: A compensating circuit for calibrating reference voltage, which is coupled to an operation amplifier having an input end and an output end within a reference voltage driving circuit, is provided in the present invention. The compensating circuit comprises a first capacitor, a second capacitor, and a first switch. The first capacitor is utilized for storing the potential with respect to the reference voltage. The second capacitor is coupled to the operation amplifier for storing the potential difference between the input end and the output end of the operation amplifier. The first switch is electrically connecting to the first capacitor and the second capacitor. When turning on the first switch, the potentials stored in the first capacitor and the second capacitor are combined and input to the operation amplifier to have an output voltage level substantially identical to the reference voltage.

Abstract: A buffer circuit for a liquid crystal display device that comprises a first transistor further comprising a gate connectable to an input signal, a first electrode coupled to a first power supply, and a second electrode connectable to a second power supply, a second transistor further comprising a gate coupled to the second electrode of the first transistor, a first electrode connectable to the first power supply, and a second electrode connectable to the second power supply, a first capacitor being connectable to the input signal storing a voltage of the input signal when connected to the input signal, and providing a first voltage to the gate of the first transistor when disconnected from the input signal, a second capacitor further comprising a terminal coupled to the second electrode of the first transistor and the gate of the second transistor providing a second voltage at the terminal when the first transistor is turned on, and a third capacitor coupled to the first electrode of the second transistor pro