Abstract: Methods and apparatus are disclosed for modifying data for use by a business. Data including one or more values are obtained. At least a portion of the data is then flagged to identify one or more business events of interest to the business. The flagged data for one or more of the identified business events is then provided, thereby enabling the identified business events to be monitored.

Abstract: Methods and apparatus for implementing a system for monitoring data for detection of events and tracking data associated with detected events are disclosed. A system for monitoring data for detection of events may include a data modification module and an event monitoring module. In one embodiment, the data modification module is adapted for obtaining data including one or more values and flagging at least a portion of the data to identify one or more attributes that together define an event. The event monitoring module is coupled to the data modification module and adapted for monitoring at least a portion of the flagged data produced by the data modification module for detection of one or more events. The system may further include a notification module adapted for sending a notification of a detected event in accordance with a set of notification preferences. Moreover, a collaboration module may be adapted for providing a graphical user interface including data associated with one or more detected events.

Abstract: A multi-film capping layer having a cobalt layer, a barrier layer, and a stuffing layer is disclosed, wherein the barrier layer isolates the cobalt layer from the stuffing layer. The multi-film capping layer is formed on a gate transistor and applicable to a self-aligned silicide (salicide) process, so that a sheet resistance of the salicide layer on conductive regions of the gate transistor is significantly reduced. The stuffing layer further prevents entry of oxygen or moisture to the salicide layer, thus no cobalt oxide is formed when RTP is performed. Without formation of the cobalt oxide, the salicide process is free from the bridging issue and the filament issue.

Abstract: The present invention provides a method and apparatus for generating the mosquito bait as well as simulating the human body's surface temperature and emanated odor. A well-controlled heating assembly can be used to generate a suitable thermal gradient for incubating both microorganisms and evaporating the bait. The bait comprises at least the bacterial decomposition and the yeast fermentation solution. The bait is not poisonous to human beings and produces mosquito attractants from natural products of fermentation or decomposition. The apparatus according to this invention comprises at least an upper compartment for trapping mosquitoes and a bottom compartment including the bait and the heating assembly. This invention can also combine with electrocution grids or insecticide webs to destroy attracted mosquitoes.

Abstract: The present invention provides a method and apparatus for generating the mosquito bait as well as simulating the human body's surface temperature and emanated odor. A well-controlled heating assembly can be used to generate a suitable thermal gradient for incubating both microorganisms and evaporating the bait. The bait comprises at least the bacterial decomposition and the yeast fermentation solution. The bait is not poisonous to human beings and produces mosquito attractants from natural products of fermentation or decomposition. The apparatus according to this invention comprises at least an upper compartment for trapping mosquitoes and a bottom compartment including the bait and the heating assembly. This invention can also combine with electrocution grids or insecticide webs to destroy attracted mosquitoes.

Abstract: A process for producing a memory structure is disclosed. According to the process, an insulating portion and a conductive portion are formed with substantially equal thickness, and arranged in an alternate way to be a field oxide structure and a floating gate structure. This can be achieved by applying a conductive layer first, creating a trench in the conductive layer, filling the trench with an insulating material, and polishing the resulting layer. Because the insulating portion is formed adjacent to the conductive portion by filling the insulating material in the trench adjacent to the conductive portion, the field oxide structure and the floating gate structure are self-aligned while forming. Accordingly, no mis-alignment occurs, and thus the integration of the device can be improved.

Abstract: The present invention relates to a dispensing device for moist towel, comprising a top cover, a push button, top board, an external cylindrical body, a blocking board, a bottom board, and a bottom cover, wherein the top cover and the bottom cover are respectively mounted at the top and the bottom of the external cylindrical body and are fastened at the cylindrical body by engaging holes at the sides of the cylindrical body, the top cover and one lateral side of the cylindrical body are provided with a sliding slot having mounted with the top board and the bottom board and the end section of the top board is provided with a triangular block and the end section of the bottom board is provided with an upward connection board having an engaging hole, and the top of the connection board is provided with an inter-linked push button, the top cover, and the center of the external cylindrical body are provided with a key hole for cutting and holding moist towel with the top and bottom board.

Abstract: A process for producing a memory structure is disclosed. According to the process, an insulating portion and a conductive portion are formed with substantially equal thickness, and arranged in an alternate way to be a field oxide structure and a floating gate structure. This can be achieved by applying a conductive layer first, creating a trench in the conductive layer, filling the trench with an insulating material, and polishing the resulting layer. Because the insulating portion is formed adjacent to the conductive portion by filling the insulating material in the trench adjacent to the conductive portion, the field oxide structure and the floating gate structure are self-aligned while forming. Accordingly, no misalignment occurs, and thus the integration of the device can be improved.

Abstract: A method of fabricating a metal plug comprises steps of providing a substrate and forming a dielectric layer on the substrate with an opening to expose part of the substrate. The method further comprises steps of forming a metal layer on the dielectric layer, forming a first barrier layer by chemical vapor deposition (CVD) to provide a better step coverage, and forming a second barrier layer by physical vapor deposition (PVD) to make the barrier layer harder and less water absorptive. A metal layer is then formed on the second barrier layer and is removed by etching back to form the metal plug.

Abstract: A method of Chisel programming in non-volatile memory by source bias. Whereby when reading and/or programming operations are executed, a body reading voltage and a body programming voltage are used. The method is comprised of changing the body programming voltage to reduce the difference between the changed body programming voltage and the body reading voltage and then running the programming operation utilizing the changed body programming voltage. Advantages include: elimination of the negative effects of parasitic capacitors in memory cells, simplification of bias circuit design, enhanced device reliability, and reduced disturbance.

Abstract: A method of forming a barrier layer is described. A dielectric layer is formed on a substrate. The dielectric layer comprises an opening exposing a portion of the substrate. A metallic layer, which is conformal to the opening, is formed on the dielectric layer. A first metallic nitride layer, which is conformal to the opening, is formed on the first metallic layer by chemical vapor deposition. The second metallic nitride layer, which is conformal to the opening, is formed on the first metallic nitride layer.

Abstract: A method of fabricating a gate junction conductive structure is described in which a selective silicon deposition method is used to form a silicon layer of a greater area on the polysilicon gate. A metal silicide process is further conducted on the silicon layer to convert the silicon layer to a metal silicide layer. Since the gate junction surface in forming the metal silicide layer is increased, not only the narrow line effect is prevented, the temperature for the thermal treatment process in forming the metal silicide layer is also lower. As a result, the sheet resistance of the metal silicide layer is lower and the device is more stable.

Abstract: A process for making self-aligned split-gate non-volatile memory cell is disclosed. It includes the step of using a nitride photomask in conjunction with a photoresist to etch the nitride layer and cause it to become a stepped nitride layer having a high thickness region and a low thickness. Then a poly-1 photomask is used in conjunction with a photoresist to etch through a first portion of the low thickness region to expose an underlying poly-1 layer intended to be floating gate, wherein at the same time, a portion of the high thickness region adjacent to the first portion of the low thickness region is also etched to a reduced thickness. After poly-1 oxidation, a cell drain photomask is used in conjunction with a photoresist to etch through a second portion of the low thickness region using a nitride etch and an underlying poly-1 layer using a poly etch.

Abstract: A technique for forming an integrated circuit device having a self-aligned gate layer. The method includes a variety of steps such as providing a substrate, which is commonly a silicon wafer. Field isolation regions including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second trench isolation regions. The isolation regions are made using a reactive ion etching technique. A thickness of material such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. The substantially planar material region is self-aligned into the recessed region using the removing step.

Abstract: A memory cell having an asymmetric source and drain connection to virtual ground bit-lines providing an abrupt junction suitable for band-to-band hot electron generation and a gradual junction suitable for Fowler-Nordheim tunneling on each side of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit line.

Abstract: A technique for forming an integrated circuit device having a self-aligned gate layer and an overlying stacked gate. The method includes a variety of steps such as providing a substrate (217), which is commonly a silicon wafer. Field isolation regions (201) including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second isolation regions. The isolation regions (201) are made using a local oxidation of silicon process, which is commonly called LOCOS, but can be others. A thickness of material (205) such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region.

Abstract: A method of fabricating a semiconductor device is described. A conductive layer is formed on a substrate. A spacer is formed on a sidewall of the conductive layer. A thin metallic layer is formed over the substrate. An ion implantation step is performed. A first seeding layer is formed between the first metallic layer and the conductive layer. A second seeding layer is formed between the first metallic layer and the substrate. A second metallic layer is formed over the substrate. An annealing step is performed to form a self-aligned silicide layer on the conductive layer. The first metallic layer and the second metallic layer that do not react are removed.

Abstract: A technique for forming an integrated circuit device having a self-aligned gate layer. The method includes a variety of steps such as providing a substrate (217), which is commonly a silicon wafer. Field isolation regions (201) including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second isolation regions. The isolation regions (201) are made using a local oxidation of silicon process, which is commonly called LOCOS, but can be others. A thickness of material (205) such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region.

Abstract: A process for making stacked gate memory cells which does not require the extra thermal cycle as in the conventional SAMOS process. It includes the steps of: (a) forming a silicon nitride layer on a wafer surface; (b) forming a diffusion pattern mask on the silicon nitride layer which includes a source line diffusion mask; (c) removing portions of the silicon nitride layer not covered by the diffusion pattern mask to expose a portion of the silicon substrate; (d) removing the diffusion pattern mask; (e) using the remaining portion of the silicon nitride as a mask to grow a field oxide layer in the silicon substrate; (f) forming a poly-1 layer, an interpoly dielectric layer, and a poly-2 layer on the wafer surface; (f) forming a SAMOS (self-aligned MOS) mask which contains a plurality of SAMOS strips perpendicular to the poly-1 strips, followed by SAMOS etching to form a plurality of stacked gates.

Abstract: An improved process for fabricating flash memory cells with high control-gate-to-floating-gate coupling ratio is disclosed. The flash memory cell contains: (a) a substrate; (b) at least a pair of spaced-apart floating gates on the substrate, each of the floating gate has a pair of poly sidewall spacers; (c) a field oxide layer (FOX) partially recessed into the substrate; (d) an oxide/nitride/oxide (ONO) layer covering each of the floating gates; (e) a control gate covering the oxide/nitride/oxide layer and the field oxide layer. The design of the flash memory cell allows the field oxide layer to be wedged between the pair of floating gates and below the poly sidewall spacers. The poly sidewall spacers substantially increases the overlapping area between the control gate and the floating gate, thus allowing the control-gate-to-floating-gate coupling ratio and the performance of the flash memory to be enhanced.