Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate; a molding surrounding the die; a dielectric layer disposed over the substrate and surrounding the die and the molding; a conductive via extending through the dielectric layer; and a metallic strip extending through and along the dielectric layer to at least partially surround the die.

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

Abstract: A method of manufacturing a semiconductor structure includes providing a substrate and a photoresist over the substrate; placing a mask over the photoresist; exposing the photoresist to a predetermined electromagnetic radiation through the mask; and removing at least a portion of the photoresist exposed to the predetermined electromagnetic radiation. The mask includes a first portion configured to totally allow the predetermined electromagnetic radiation passing through, a second portion configured to partially allow the predetermined electromagnetic radiation passing through, and a third portion configured to block the predetermined electromagnetic radiation, the second portion is disposed between the first portion and the third portion.

Abstract: The present disclosure provides a method for preparing a semiconductor structure. The method includes the following steps. A substrate including a conductive layer formed thereon is provided. The conductive layer is patterned to form a plurality of conductive patterns extending along a first direction. A cap layer is conformally formed to cover the plurality of conductive patterns. A patterned hard mask is formed over the cap layer. The plurality of conductive patterns are etched through the patterned hard mask to form a plurality of conductive islands. In some embodiments, the plurality of conductive islands are separated from each other by a plurality of first gaps along the first direction. In some embodiments, the plurality of conductive islands are separated from each other by the cap layer and a plurality of second gaps along a second direction that is different from the first direction.

Abstract: The present disclosure provides a method for preparing a semiconductor structure. The method includes the following steps. A mask stack including a first mask and a second mask is formed on a substrate. A plurality of third masks are formed. A patterned layer including first openings is formed. Portions of the second mask are removed through the first openings and the third masks to form second openings, and portions of the first mask are exposed through the second openings. A plurality of self-aligned protecting structures are formed in the second openings. Portions of the second mask exposed through the third masks are removed to form third openings, and portions of the first mask are exposed through the third openings. The portions of the first mask are removed to form a hybrid hard mask. The substrate is etched through the hybrid hard mask to form a plurality of recesses.

Abstract: A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. The first molding compound is disposed over the first redistribution layer and surrounds the semiconductor device. The second molding compound surrounds the first redistribution layer and at least a part of the first molding compound. The conductive vias extend through the second molding compound. The second redistribution layer is disposed on a surface of the second molding compound away from the first redistribution layer. The second redistribution layer is electrically connected to the first redistribution layer through the conductive vias.

Abstract: The present disclosure provides a method for preparing semiconductor structures. The method includes the following steps. A substrate is provided. A plurality of first trenches are formed in the substrate. A first initially-flowable layer is formed in the plurality of first trenches. A top surface of the first initially-flowable layer is lower than openings of the plurality of first trenches. A first treatment is performed on the first initially-flowable layer to form a first dielectric layer in the plurality of first trenches. A second initially-flowable layer is formed to fill the plurality of first trenches. A second treatment is performed on the second initially-flowable layer to form a second dielectric layer in the plurality of first trenches.

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

Abstract: A method for preparing a semiconductor structure includes the following steps: providing a substrate including a first region and a second region defined thereon, forming a first mask structure over the substrate, forming a plurality of first features in the first mask structure in the first region, forming a second mask structure over the first mask structure, simultaneously forming a plurality of second features in the second mask structure in the second region and a plurality of third features in the second mask structure in the first region, and transferring the second features and the third features to the first mask structure to simultaneously form a plurality of islanding features in the first region and a plurality of line features in the second region.

Abstract: A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.

Abstract: A method for preparing a semiconductor structure includes the following steps. A target layer is formed over a substrate. A first patterned mask is formed over the target layer and includes plural first openings separate from each other. The first openings are filled with a first sacrificial layer. A patterned core layer is formed on the first sacrificial layer and includes plural closed patterns and plural second openings within the closed patterns of the patterned core layer. Plural spacers are formed on sidewalls of the patterned core layer. The spacers are removed to form a plurality of third openings over the substrate. The first sacrificial layer and the first patterned mask are etched through the third openings. The first sacrificial layer is removed to form a second patterned mask on the target layer. The target layer is etched through the second patterned mask to form a patterned target layer.

Abstract: A method of manufacturing semiconductor device is provided in the present disclosure. The method includes forming a first pattern layer on a first area of a substrate, forming a spin on layer on the first pattern layer and the substrate, forming an etch stop layer on the spin on layer, and forming a first mask layer on the etch stop layer.

Abstract: A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

Abstract: A method of manufacturing semiconductor device is provided in the present disclosure. The method includes forming a first pattern layer on a first area of a substrate, forming a spin on layer on the first pattern layer and the substrate, forming an etch stop layer on the spin on layer, and forming a first mask layer on the etch stop layer.

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

Abstract: A method of manufacturing a semiconductor structure includes forming a lower hard mask layer on a substrate. A patterned middle hard mask layer is formed on the lower hard mask layer, and the patterned middle hard mask layer has a plurality of openings exposing a portion of the lower hard mask layer. A patterned lower hard mask layer and a textured substrate having a plurality of trenches are formed by etching the exposed portion of the lower hard mask layer and a portion of the substrate under the exposed portion of the lower hard mask layer. A steam treatment is then performed on the textured substrate having the trenchess. An isolation oxide layer is formed to fill the trenches.

Abstract: A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. The first molding compound is disposed over the first redistribution layer and surrounds the semiconductor device. The second molding compound surrounds the first redistribution layer and at least a part of the first molding compound. The conductive vias extend through the second molding compound. The second redistribution layer is disposed on a surface of the second molding compound away from the first redistribution layer. The second redistribution layer is electrically connected to the first redistribution layer through the conductive vias.

Abstract: The present disclosure provides a method for preparing semiconductor structures. The method includes the following steps. A substrate is provided. A plurality of first trenches, a plurality of second trenches, a plurality of first island structures and a plurality of second island structures are formed. Each of the first island structures is separated from each of the second island structures by the first trenches. The plurality of first island structures are separated from each other by the second trenches, and the plurality of second island structures are separated from each other by the second trenches. A first dielectric layer is then conformally formed to cover sidewalls and a bottom of each first trench and sidewalls and a bottom of each second trench. A semiconductor layer is formed on the first dielectric layer. An oxidation is performed to convert the semiconductor layer into a semiconductor oxide layer in each of the first trenches and each of the second trenches.

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.