Patents by Inventor Shing-Yih Shih

Shing-Yih Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR STRUCTURE
    Publication number: 20210125910
    Abstract: A semiconductor structure includes a first component and a second component bonded thereof. The first component includes a first interlayer dielectric (ILD) layer, a first interconnect structure, a first seal ring, and a first bonding layer. The first interconnect structure is in the first ILD layer and surrounded by the first seal ring. The first bonding layer covers the first ILD layer and the first interconnect structure, and has a portion surrounds the first seal ring. The second component includes a second ILD layer, a second interconnect structure, a second seal ring, and a second bonding layer. The second interconnect structure is in the second ILD layer and surrounded by the second seal ring. The second bonding layer is in contact with the first bonding layer and covers the second ILD layer and the second interconnect structure, and has a portion surrounds the second seal ring.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 29, 2021
    Inventors: Shing-Yih SHIH, Tse-Yao HUANG
  • Semiconductor device and manufacture method thereof
    Patent number: 10978338
    Abstract: A semiconductor device includes substrate, arrays, conductive structures, and liner spacer layer is provided. The substrate has array region and peripheral region. The arrays are disposed on the array region, and have conductive pillars. The conductive structures are located on the peripheral region, and have at least one connecting sidewall. The liner spacer layer covers the conductive pillars and the conductive structures. Sidewalls of the conductive pillars of the arrays facing a first direction and the connecting sidewall of the conductive structure are free from the liner spacer layer. The conductive pillars are arranged along a second direction in the array, and the second direction is different from the first direction. The liner spacer layer covering the arrays and the conductive structures are extended from the substrate. A manufacturing method of the semiconductor device is also provided.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 13, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • SEMICONDUCTOR DEVICE
    Publication number: 20210098461
    Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a dummy region surrounding the cell region, a plurality of memory pillar structures, and a supporting layer. The memory pillar structures are on the cell region. The supporting layer is over the semiconductor substrate, interconnecting the memory pillar structures, and having a plurality of first and second opening patterns on the cell region. A first number of the memory pillar structures surround each of the first opening patterns, and a second number of the memory pillar structures surround each of the second opening patterns. The first opening patterns are different from the second opening patterns, the first number is different from the second number, and at least one of the first opening patterns and at least one of the second opening patterns are on a central portion of the cell region.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 1, 2021
    Inventors: Shing-Yih SHIH, Tse-Yao HUANG
  • WAFER LEVEL PACKAGE UTILIZING MOLDED INTERPOSER
    Publication number: 20210090985
    Abstract: Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.
    Type: Application
    Filed: December 2, 2020
    Publication date: March 25, 2021
    Inventor: Shing-Yih Shih
  • Methods of forming microelectronic devices having a patterned surface structure
    Patent number: 10950564
    Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Tieh-Chiang Wu
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10950538
    Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate; a molding surrounding the die; a dielectric layer disposed over the substrate and surrounding the die and the molding; a conductive via extending through the dielectric layer; and a metallic strip extending through and along the dielectric layer to at least partially surround the die.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 16, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Methods of forming microelectronic devices including dummy dice
    Patent number: 10937749
    Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Neng-Tai Shih
  • MICROELECTRONIC DEVICES INCLUDING EMBEDDED BRIDGE INTERCONNECT STRUCTURES
    Publication number: 20210050327
    Abstract: A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.
    Type: Application
    Filed: November 3, 2020
    Publication date: February 18, 2021
    Inventor: Shing-Yih Shih
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210043545
    Abstract: A semiconductor device includes a first semiconductor wafer, a second semiconductor wafer, and a first conductive via. The first semiconductor wafer includes a first substrate and at least one first conductive layer disposed on a top surface of the first substrate. The second semiconductor wafer is disposed on the first semiconductor wafer. The second semiconductor wafer includes a second substrate and a first conductive pad disposed on a top surface of the second substrate. The first conductive via extends from the first conductive pad to the first conductive layer.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Sheng-Fu HUANG, Shing-Yih SHIH
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210035905
    Abstract: The semiconductor structure includes a first die, a second die, a connecting portion, and a through-substrate via. The first die includes a first dielectric layer and a first helical conductor embedded therein. The second die includes a second dielectric layer and a second helical conductor embedded therein, wherein the second dielectric layer is bonded with the first dielectric layer, thereby forming an interface. The connecting portion extends from the first dielectric layer through the interface to the second dielectric layer and interconnects the first helical conductor with the second helical conductor. The through-substrate via extends from the first die to the second die through the interface, wherein the through-substrate via is surrounded by the first and the second helical conductors.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 4, 2021
    Inventor: Shing-Yih SHIH
  • Semiconductor package including hybrid bonding structure and method for preparing the same
    Patent number: 10910357
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a first die, a second die and a hybrid bonding structure disposed between the first die and the second die. The first die includes a first front side and a first back side opposite to the first front side. The second die includes a second front side and a second back side opposite to the second front side. The hybrid bonding structure is disposed between the first back side of the first die and the second front side of the second die. The first die and the second die are bonded to each other by the hybrid bonding structure. The hybrid bonding structure includes an organic barrier layer and an inorganic barrier layer bonded to each other.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: February 2, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20210028121
    Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface and a back surface, at least one semiconductor device, a first TSV disposed in the substrate, an insulating layer surrounding the first TSV, a shielding layer surrounding the insulating layer, and a second TSV adjacent to the first TSV. The semiconductor device is disposed in a device region of the substrate. The first TSV is exposed by the front surface and the back surface of the substrate. The insulating layer includes an electrically insulating material. The shielding layer includes an electrically conductive material coupled to ground through a ground layer. The second TSV is exposed by the front surface and the back surface of the substrate.
    Type: Application
    Filed: July 24, 2019
    Publication date: January 28, 2021
    Inventors: SHING-YIH SHIH, TSE-YAO HUANG
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210028053
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first set conductive elements separately positioned above the semiconductor substrate, a plurality of insulating blocks respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements, a plurality of first set supporting pillars respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements and respectively correspondingly positioned over the plurality of insulating blocks, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars and respectively correspondingly positioned over the plurality of insulating blocks.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 28, 2021
    Inventors: TSE-YAO HUANG, SHING-YIH SHIH
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210028103
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first conductive elements separately positioned above the semiconductor substrate, a plurality of first supporting pillars respectively correspondingly positioned between an adjacent pairs of the plurality of first set conductive elements, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 28, 2021
    Inventors: TSE-YAO HUANG, SHING-YIH SHIH
  • Method of forming fine interconnection for a semiconductor device
    Patent number: 10903110
    Abstract: A method of forming fine interconnection includes: forming spacers on a first and second hard mask layer on a dielectric layer; forming a first via hole through the first hard mask layer, the second hard mask layer, and the dielectric layer; oxidizing a sidewall of the first hard mask layer that surrounding the via hole; forming a second via hole in the second hard mask layer; forming a mask to cover the first hard mask layer in the second via hole; forming a line trench in a portion of the second hard mask layer exposed by the spacers and the mask, and in the first hard mask layer and the dielectric layer that are below the portion of the second hard mask layer; and forming a conductive material in the line trench and the first via hole.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 26, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • CONDUCTIVE VIA STRUCTURE
    Publication number: 20210020455
    Abstract: A conductive via structure includes a first dielectric layer, a conductive pad, a second dielectric layer, and a redistribution layer. The conductive pad is in the first dielectric layer. The second dielectric layer is disposed above the first dielectric layer and has an opening. The conductive pad is in the opening. The opening has a first width at a top surface of the second dielectric layer and a second width at a bottom surface of the second dielectric layer. A difference between the first width and the second width is in a range from about 1.5 um to about 3 um. The redistribution layer extends from the top surface of the second dielectric layer to the conductive pad.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Inventor: Shing-Yih SHIH
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20200411367
    Abstract: A semiconductor structure includes a semiconductor device, an interconnect structure, a dielectric layer, and a redistribution layer (RDL). The interconnect structure is disposed over the semiconductor device. The dielectric layer is disposed over the interconnect structure. The RDL includes a conductive structure over the dielectric layer and a conductive via extending downwards from the conductive structure and through the dielectric layer. The conductive via includes a bottom portion, a top portion and a tapered portion between the bottom and top portions, in which the tapered portion has a width variation greater than that of the bottom and top portions.
    Type: Application
    Filed: September 13, 2020
    Publication date: December 31, 2020
    Inventors: Shing-Yih SHIH, Chih-Ching LIN
  • Wafer level package utilizing molded interposer
    Patent number: 10872852
    Abstract: A molded interposer includes a layer of first molding compound having a first side and a second side opposite to the first side; a first redistribution layer (RDL) structure disposed on the first side; a second redistribution layer (RDL) structure disposed on the second side; a plurality of metal vias embedded in the layer of first molding compound for electrically connecting the first RDL structure with the second RDL structure; and a passive device embedded in the layer of first molding compound.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih
  • SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20200395242
    Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.
    Type: Application
    Filed: June 12, 2019
    Publication date: December 17, 2020
    Inventors: Shing-Yih SHIH, Mao-Ying WANG, Hung-Mo WU
  • Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods
    Patent number: 10833052
    Abstract: A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih