Abstract: The present application discloses a semiconductor device with protection layers for reducing the metal to silicon leakage and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a conductive filler layer positioned along the first mask layer and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die and between the conductive filler layer and the second die, and protection layers positioned between the conductive filler layer and the first mask layer and covering upper portions of the isolation layers.

Abstract: The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor device structure includes a conductive structure disposed over a semiconductor substrate, and a conductive plug disposed over the conductive structure. The conductive plug is electrically connected to the conductive structure. The semiconductor device structure also includes a first spacer formed on a sidewall surface of the conductive plug, and an etch stop layer disposed over the semiconductor substrate. The etch stop layer adjoins the first spacer. The semiconductor device further includes a first inter-layer dielectric (ILD) layer disposed over the etch stop layer and next to the conductive plug, wherein the first ILD layer is separated from the first spacer by an air gap.

Abstract: A semiconductor structure includes a first wafer, a conductive via, an isolation layer, and a spacer structure. The first wafer includes a semiconductor substrate, a multi-level interconnect structure, and a dielectric layer. The semiconductor substrate has a front side and a back side. The multi-level interconnect structure is disposed over the front side of the semiconductor substrate. The dielectric layer is disposed over the back side of the semiconductor substrate. The conductive via extends from the dielectric layer to a conductive line of the multi-level interconnect structure. The isolation layer is disposed between the conductive via and the first wafer. The spacer structure is disposed between the conductive via and the isolation layer, in which the spacer structure is spaced apart from the conductive line.

Abstract: A semiconductor structure includes a first wafer, a conductive via, an isolation layer, and a spacer structure. The first wafer includes a semiconductor substrate, a multi-level interconnect structure, and a dielectric layer. The semiconductor substrate has a front side and a back side. The multi-level interconnect structure is disposed over the front side of the semiconductor substrate. The dielectric layer is disposed over the back side of the semiconductor substrate. The conductive via extends from the dielectric layer to a conductive line of the multi-level interconnect structure. The isolation layer is disposed between the conductive via and the first wafer. The spacer structure is disposed between the conductive via and the isolation layer, in which the spacer structure is spaced apart from the conductive line.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first set conductive elements separately positioned above the semiconductor substrate, a plurality of insulating blocks respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements, a plurality of first set supporting pillars respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements and respectively correspondingly positioned over the plurality of insulating blocks, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars and respectively correspondingly positioned over the plurality of insulating blocks.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a second mask layer positioned on the first mask layer, a conductive filler layer positioned penetrating the second mask layer, the first mask layer, and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die, between the conductive filler layer and the second die, and between the conductive filler layer and the first mask layer, and protection layers positioned between the conductive filler layer and the second mask layer and between the conductive filler layer and the first mask layer, and covering upper portions of the isolation layers.

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, an encapsulant and a through encapsulant via. The semiconductor die includes a semiconductor substrate, an interconnection layer and a through semiconductor via. The semiconductor substrate has an active surface and a back surface opposite to the active surface. The interconnection layer is disposed over the active surface of the semiconductor substrate. The through semiconductor via penetrates through the semiconductor substrate from the back surface of the semiconductor substrate to the active surface of the semiconductor substrate. The semiconductor die is encapsulated by the encapsulant. The through encapsulant via penetrates through the encapsulant.

Abstract: The semiconductor structure includes a first die, a second die, a connecting portion, and a through-substrate via. The first die includes a first dielectric layer and a first helical conductor embedded therein. The second die includes a second dielectric layer and a second helical conductor embedded therein, wherein the second dielectric layer is bonded with the first dielectric layer, thereby forming an interface. The connecting portion extends from the first dielectric layer through the interface to the second dielectric layer and interconnects the first helical conductor with the second helical conductor. The through-substrate via extends from the first die to the second die through the interface, wherein the through-substrate via is surrounded by the first and the second helical conductors.

Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

Abstract: A semiconductor assembly comprises a first device, a second device, a passivation layer and an interconnect structure. The first device comprises a first top metal layer. The second device comprises a second bottom metal layer. The passivation layer is disposed on the second device. The interconnect structure electrically couples the first device to the second device, wherein the interconnect structure comprises a head member, a first leg and a second leg. The head member is disposed on the passivation layer. The first leg penetrates through the passivation layer and the second device, wherein the first leg connects the head member to the first top metal layer. The second leg penetrates through the passivation layer and extends into the second device to connect the head member to the second bottom metal layer. The first leg and the second leg comprise a top portion, an intermediate portion and a bottom portion.

Abstract: A semiconductor device includes a conductive pattern disposed over a semiconductor substrate, and an interconnect structure disposed over the conductive pattern. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.

Abstract: A semiconductor structure includes a first substrate, a second substrate, a metal layer, a buffer structure, and a barrier structure. The first substrate has a landing pad. The second substrate is disposed over the first substrate. The metal layer is disposed in the second substrate and extends from the landing pad to a top surface of the second substrate. The buffer structure is disposed in the second substrate and surrounded by the metal layer, in which a top surface of the buffer structure is below a top surface of the metal layer. The barrier structure is disposed over the metal layer and the buffer structure.

Abstract: A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.

Abstract: The present disclosure provides a semiconductor assembly and method of manufacturing the same. The semiconductor assembly includes a semiconductor device, a bulk semiconductor, a passivation layer, at least one conductive plug, a plurality of protective liners, and a plurality of isolation liners. The bulk semiconductor is disposed over the semiconductor device. The passivation layer covers the bulk semiconductor. The conductive plug comprises a first block disposed in the passivation layer and a second block disposed between the first block and the conductive pad, wherein portions of peripheries of the first and second blocks of the conductive plug are surrounded by the protective liners and the isolation liners.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a first connecting structure positioned on the first semiconductor structure, and a second semiconductor structure positioned on the first connecting structure. The first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, a plurality of first connecting contacts positioned in the first connecting insulating layer, and a plurality of first supporting contacts positioned in the first connecting insulating layer. The top surfaces of the plurality of first connecting contacts contact a bottom surface of the second semiconductor structure. A top surface of the plurality of first connecting contact and a top surface of the plurality of first supporting contact protrude from a top surface of the first connecting insulating layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a first connecting structure, and a second semiconductor structure positioned on the first connecting structure. The first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. The second semiconductor structure is positioned on the first connecting structure and includes two second conductive features positioned on the two first conductive layers. The first conductive layer has a first width, the second conductive feature has a second width greater than the first width, and the different width forms a step-shaped cross-sectional profile near an interface of the first conductive layer and the second conductive feature.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a first connecting structure positioned on the first semiconductor structure, and a second semiconductor structure positioned on the first connecting structure. The first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, a plurality of first connecting contacts positioned in the first connecting insulating layer, and a plurality of first supporting contacts positioned in the first connecting insulating layer. The top surfaces of the plurality of first connecting contacts contact a bottom surface of the second semiconductor structure. A top surface of the plurality of first connecting contact and a top surface of the plurality of first supporting contact protrude from a top surface of the first connecting insulating layer.

Abstract: The present disclosure provides a semiconductor assembly and method of manufacturing the same. The semiconductor assembly includes a semiconductor device, a bulk semiconductor, a passivation layer, at least one conductive plug, a plurality of protective liners, and a plurality of isolation liners. The bulk semiconductor is disposed over the semiconductor device. The passivation layer covers the bulk semiconductor. The conductive plug comprises a first block disposed in the passivation layer and a second block disposed between the first block and the conductive pad, wherein portions of peripheries of the first and second blocks of the conductive plug are surrounded by the protective liners and the isolation liners.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a first region, and a first transistor positioned in the first region. The first transistor includes a first bottom gate structure positioned on the substrate, a first channel layer positioned on the first bottom gate structure, a first top gate structure positioned on the first channel layer, and two first source/drain regions positioned on two sides of the first channel layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a first connecting structure, and a second semiconductor structure positioned on the first connecting structure. The first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. The second semiconductor structure is positioned on the first connecting structure and includes two second conductive features positioned on the two first conductive layers. The first conductive layer has a first width, the second conductive feature has a second width greater than the first width, and the different width forms a step-shaped cross-sectional profile near an interface of the first conductive layer and the second conductive feature.