Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210064520
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.
    Type: Application
    Filed: March 11, 2020
    Publication date: March 4, 2021
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210064287
    Abstract: According to one embodiment, a memory system detects a first block in which an elapsed time from a time point at which the block has been filled with write data exceeds a first period. The memory system notifies a host of a list of identifiers capable of identifying valid data portions stored in the first block or a list of identifiers capable of identifying all data portions stored in the first block. When receiving, from the host, a first copy request specifying one or more valid data portions stored in the first block as copy target data and specifying the second block group as a copy destination block group, the memory system copies the one or more valid data portions specified as the copy target data from the first block to the second block group.
    Type: Application
    Filed: March 11, 2020
    Publication date: March 4, 2021
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • Memory system and method of controlling nonvolatile memory
    Patent number: 10936226
    Abstract: According to one embodiment, when data is to be written to a first physical storage location that is designated by a first physical address, a memory system encrypts the data with the first physical address and a first encryption key, and writes the encrypted data to the first physical storage location. When the encrypted data is to be copied to a second physical storage location, the memory system decrypts the encrypted data with the first physical address and the first encryption key, and re-encrypts the decrypted data with a second encryption key and a copy destination physical address indicative of the second physical storage location.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Storage system capable of invalidating data stored in a storage device thereof
    Patent number: 10936252
    Abstract: A storage device includes a non-volatile semiconductor storage device including a plurality of physical blocks, and a controller. The controller is configured to maintain a mapping of logical addresses to locations within the physical blocks, send, to a host, a first list that contains logical addresses corresponding to one or more target physical block that are targeted for garbage collection, and then receive, from the host, a second list that contains one or more logical addresses in the first list, and invalidate data stored in the logical addresses in the second list prior to the garbage collection.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: March 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Hashimoto, Shinichi Kanno
  • Nonvolatile memory system and method for controlling write and read operations in the nonvolatile memory by a host
    Patent number: 10929067
    Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: February 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM, HOST DEVICE AND INFORMATION PROCESSING SYSTEM FOR ERROR CORRECTION PROCESSING
    Publication number: 20210042033
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida, Hiroshi Murayama
  • SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES TO ALLOCATE BLOCKS TO A MEMORY AND RELEASE ALLOCATED BLOCKS
    Publication number: 20210042034
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
  • Memory device and non-transitory computer readable recording medium
    Patent number: 10901885
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 26, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM
    Publication number: 20200409555
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Hiroshi YAO, Shinichi KANNO, Kazuhiro FUKUTOMI
  • Memory system having a plurality of writing modes
    Patent number: 10877664
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: December 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Yao, Shinichi Kanno, Kazuhiro Fukutomi
  • MEMORY SYSTEM FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20200401311
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Shinichi KANNO
  • Memory system and method of controlling memory system
    Patent number: 10871900
    Abstract: According to one embodiment, a memory system comprises a non-volatile semiconductor memory having a plurality of first storage areas, the first storage areas being capable of including one or more second storage areas, a plurality of third storage areas in which data is written in a first mode, and a plurality of fourth storage areas in which data is written in a second mode, the first mode being different from the second mode, and processing circuitry.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Yao, Shinichi Kanno, Kazuhiro Fukutomi
  • Memory system, host device and information processing system for error correction processing
    Patent number: 10866733
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida, Hiroshi Murayama
  • Storage device that secures a block for a stream or namespace and system having the storage device
    Patent number: 10860230
    Abstract: A storage device includes a nonvolatile semiconductor memory device including a plurality of physical blocks and a memory controller. The memory controller is configured to associate one or more physical blocks to each of a plurality of stream IDs, execute a first command containing a first stream ID received from a host, by storing write data included in the write IO in the one or more physical blocks associated with the first stream ID, and execute a second command containing a second stream ID received from the host, by selecting a first physical block that includes valid data and invalid data, transfer the valid data stored in the first physical block to a second physical block, and associate the first physical block from which the valid data has been transferred, with the second stream ID.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 8, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Daisuke Hashimoto, Shinichi Kanno
  • Memory system for controlling nonvolatile memory
    Patent number: 10861580
    Abstract: According to one embodiment, a memory system controls a plurality of parallel access units each of which includes a plurality of blocks belonging to the different nonvolatile memory chips. The memory system stores information indicating address conversion rules prescribed such that the number of defective blocks included in the parallel access units is equal to or smaller than a first number. Each of the address conversion rules indicates a mathematical rule for converting a block address to be sent to each of the nonvolatile memory chips into another block address. An address conversion circuit in the memory system converts each of block addresses to be sent to each nonvolatile memory chip into another block address, based on each mathematical rule.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • CONTROLLER, DATA STORAGE DEVICE, AND PROGRAM PRODUCT
    Publication number: 20200379901
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO
  • Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks
    Patent number: 10845992
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 24, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • INFORMATION PROCESSING APPARATUS AND METHOD FOR CONTROLLING STORAGE DEVICE
    Publication number: 20200364145
    Abstract: According to one embodiment, an information processing apparatus stores first data to be written to one destination block of a nonvolatile memory in a write buffer on a memory of the information processing apparatus. The information processing apparatus transmits, to a storage device, a write request including a first identifier associated with the one write destination block and storage location information indicating a location in the write buffer in which the first data is stored. The information processing apparatus transfers the first data from the write buffer to the storage device every time a transfer request including the storage location information is received from the storage device.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 19, 2020
    Inventors: Shinichi Kanno, Hideki Yoshida
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20200363996
    Abstract: According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to be written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.
    Type: Application
    Filed: August 4, 2020
    Publication date: November 19, 2020
    Inventors: Shinichi Kanno, Hideki Yoshida
  • MEMORY SYSTEM AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM
    Publication number: 20200364140
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, configuration unit, address translation unit, write unit and control unit. The configuration unit assigns write management areas included in a nonvolatile memory to spaces and an input space. The write management area is a unit of an area which manages the number of write. The address translation unit associates a logical address of write data with a physical address which indicates a position of the write data in the nonvolatile memory. The write unit writes the write data to the input space and then writes the write data in the input space to a space corresponding to the write data amongst the spaces. The control unit controls the spaces individually with respect to the nonvolatile memory.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 19, 2020
    Inventor: Shinichi Kanno