Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220057966
    Abstract: According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.
    Type: Application
    Filed: March 16, 2021
    Publication date: February 24, 2022
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20220058117
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Application
    Filed: October 12, 2021
    Publication date: February 24, 2022
    Inventors: Shinichi KANNO, Hideki YOSHIDA
  • MEMORY SYSTEM AND WRITE CONTROL METHOD
    Publication number: 20220043604
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory is correspond to a first mode of writing data of N bits per unit area and a second mode of writing data of M bits (M>N) per unit area. When receiving a first command issued prior to a write command to instruct writing write data to the nonvolatile memory, the controller selects one or both of the first mode and the second mode for writing the write data to the nonvolatile memory, to allow writing the write data to the nonvolatile memory to be executed in the first mode as much as possible, based on a capacity of the write data specified by the first command and a capacity of a free area of the nonvolatile memory.
    Type: Application
    Filed: June 4, 2021
    Publication date: February 10, 2022
    Applicant: Kioxia Corporation
    Inventors: Takahiro KURITA, Shinichi KANNO
  • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20220035702
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
    Type: Application
    Filed: October 5, 2021
    Publication date: February 3, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Kenichiro YOSHII, Shinichi KANNO
  • System and method of writing to nonvolatile memory using write buffers
    Patent number: 11237756
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 1, 2022
    Assignee: Toshiba Memory Coiporation
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka
  • Memory system and control method
    Patent number: 11237759
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller is electrically coupled to the nonvolatile memory. The controller controls the nonvolatile memory. When receiving, from the host, a first command for changing a state of an allocated block to a reallocatable state in a case where a second command that is yet to be executed or being executed involving read of data from the allocated block has been received from the host, the controller changes the state of the allocated block to the reallocatable state after the second command is finished.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: February 1, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Storage system, information processing system and method for controlling nonvolatile memory
    Patent number: 11237764
    Abstract: According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: February 1, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Memory system and method of controlling nonvolatile memory
    Patent number: 11237769
    Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 1, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM
    Publication number: 20220011964
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.
    Type: Application
    Filed: March 15, 2021
    Publication date: January 13, 2022
    Applicant: Kioxia Corporation
    Inventors: Yuki SASAKI, Shinichi KANNO
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY WITH CHECKING A TOTAL SIZE INDICATIVE OF A SUM OF DATA LENGTH SPECIFIED BY A WRITE COMMAND
    Publication number: 20220011981
    Abstract: According to one embodiment, a memory system checks a first total size indicative of a sum of data lengths specified by first write commands stored in a first submission queue of a host corresponding to a first stream. When the first total size is greater than or equal to a minimum write size, the memory system fetches a set of first write commands stored in the first submission queue, transfers first write data associated with the set of first write commands from a memory of the host to the memory system, and writes the first write data into a first write destination block allocated for the first stream.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • Memory system for controlling nonvolatile memory
    Patent number: 11221914
    Abstract: According to one embodiment, a memory system copies content of a first logical-to-physical address translation table corresponding to a first region of a nonvolatile memory to a second logical-to-physical address translation table corresponding to a second region of the nonvolatile memory. When receiving a read request specifying a logical address in the second region, the memory system reads a part of the first data from the first region based on the second logical-to-physical address translation table. The memory system detects a block which satisfies a refresh condition from a first group of blocks allocated to the first region, corrects an error of data of the detected block and writes the corrected data back to the detected block.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: January 11, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Memory system controlling nonvolatile memory
    Patent number: 11216188
    Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: January 4, 2022
    Assignee: Kioxia Corporation
    Inventors: Naoki Esaka, Shinichi Kanno
  • Memory system and method of controlling memory system
    Patent number: 11216185
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 4, 2022
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Yao, Shinichi Kanno, Kazuhiro Fukutomi
  • STORAGE DEVICE, STORAGE SYSTEM, AND CONTROL METHOD
    Publication number: 20210405900
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to select a first mode as a write mode to write data from the host to the nonvolatile memory when the controller receives a first instruction from the host. In the first mode, n-bit data is written into a memory cell in a first area of the nonvolatile memory, n being a positive integer more than or equal to 1. The controller is configured to select another mode different from the first mode as the write mode when the controller receives a second instruction from the host.
    Type: Application
    Filed: March 15, 2021
    Publication date: December 30, 2021
    Applicant: Kioxia Corporation
    Inventors: Takahiro KURITA, Tetsuya SUNATA, Shinichi KANNO
  • COMPUTING SYSTEM AND METHOD FOR CONTROLLING STORAGE DEVICE
    Publication number: 20210406173
    Abstract: According to one embodiment, a computing system transmits to a storage device a write request designating a first logical address for identifying first data to be written and a length of the first data. The computing system receives from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block by the storage device, and a first physical storage location in the first block to which the first data is written. The computing system updates a first table which manages mapping between logical addresses and physical addresses of the storage device and maps the first physical address to the first logical address.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210382648
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA, Hiroshi NISHIMURA
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY BY CONTROLLING THE WRITING OF DATA TO AND READING OF DATA FROM A PLURALITY OF BLOCKS IN THE NONVALATILE MEMORY
    Publication number: 20210373814
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks and a controller configured to write data to a plurality of write destination blocks allocated from the plurality of blocks. The controller is configured to in response to receiving a read command from a host, increment a first counter value corresponding to a first block having a block address allocated to a logical address of read target data specified by the received read command. The controller is configured to read the read target data from the first block or a buffer depending on whether the read target data is readable from the first block, and decrement the first counter value corresponding to the first block. The controller is configured to prohibit processing for transitioning a state of a block associated with an uncompleted read command to a state reusable as a new write destination block.
    Type: Application
    Filed: August 11, 2021
    Publication date: December 2, 2021
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • Memory system and method of controlling nonvolatile memory
    Patent number: 11176032
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 16, 2021
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210349632
    Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Nonvolatile semiconductor memory device
    Patent number: 11169875
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: November 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Kenichiro Yoshii, Shinichi Kanno