Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY SYSTEM THAT CONSTRUCTS VIRTUAL STORAGE REGIONS FOR VIRTUAL MACHINES
    Publication number: 20210200442
    Abstract: A memory system connectable to a host includes a nonvolatile memory and a controller. The controller is configured to generate one or more virtual storage regions each of which is associated with a virtual machine running in the host, using physical memory regions of the nonvolatile memory, maintain a threshold value for each of said one or more virtual storage regions, determine a cumulative amount of data that have been written in each of said one or more virtual storage regions, and restrict writing of data with respect to a virtual storage region for which the cumulative amount exceeds the threshold value.
    Type: Application
    Filed: March 16, 2021
    Publication date: July 1, 2021
    Inventor: Shinichi KANNO
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11042305
    Abstract: According to one embodiment, a memory system manages wear of each of a plurality of blocks in a nonvolatile memory. The memory system receives, from a host, a write request including a parameter specifying a data retention term required for first data to be written. The memory system selects, from the blocks, a first block in which a data retention term estimated from the wear of the first block is longer than or equal to the specified data retention term. The memory system writes the first data to the first block.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 22, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11042487
    Abstract: According to one embodiment, a memory system receives a write request specifying a first logical address to which first data is to be written, and a length of the first data, from a host. The memory system writes the first data to a nonvolatile memory, and stores a first physical address indicating a physical storage location on the nonvolatile memory to which the first data is written, and the length of the first data, in an entry of a logical-to-physical address translation table corresponding to the first logical address. When the memory system receives a read request specifying the first logical address, the memory system acquires the first physical address and the length from the address translation table, and reads the first data from the nonvolatile memory.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 22, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Memory device managing data in accordance with command and non-transitory computer readable recording medium
    Patent number: 11042331
    Abstract: According to one embodiment, a memory device includes a first memory, a control circuit controlling the first memory, and a second memory storing a second program. The second program manages management information associated with the first memory, sends the management information conforming to a specific interface to a first program if a command conforming to the specific interface is an output command to output the management information. The second program receives first information conforming to the specific interface and issued by the first program, translates the first information into second information corresponding to the second program, translates the second information into third information corresponding to the control circuit, and executes processing for the first memory in accordance with the third information.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 22, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida
  • Semiconductor memory device and method of controlling the same
    Patent number: 11038536
    Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: June 15, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hironori Uchikawa
  • LIGATION DEVICE
    Publication number: 20210161535
    Abstract: In a ligation device for performing ligation by inserting a string-shaped body wound around a target into a tubular body, an object is to provide a ligation device that does not require a special instrument during the insertion of the string-shaped body and offers excellent workability. A means for solving the problem is a ligation device 1 for ligating a target V. The ligation device 1 includes a tubular body 2 having a tubular shape and including a hollow part 5 into which a string-shaped body 20 can be inserted. The tubular body 2 includes a proximal opening and a distal opening at a proximal end part 3 and a distal end part 4, respectively. The proximal opening and the distal opening communicate with each other via a lumen 5 of the tubular body 2. The side of a first end part 21 of the string-shaped body 20 can be inserted into the hollow part 5.
    Type: Application
    Filed: May 25, 2020
    Publication date: June 3, 2021
    Applicant: FORCE ENGINEERING CO., LTD.
    Inventors: Takanori IMAI, Takaki SAWAHATA, Hiroshi HIROTA, Shinichi KANNO, Shinichi ONO, Tomoyuki SAWAHATA, Tomohiro MURAKAMI, Tomoaki HIGUCHI
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210165571
    Abstract: According to one embodiment, when data is to be written to a first physical storage location that is designated by a first physical address, a memory system encrypts the data with the first physical address and a first encryption key, and writes the encrypted data to the first physical storage location. When the encrypted data is to be copied to a second physical storage location, the memory system decrypts the encrypted data with the first physical address and the first encryption key, and re-encrypts the decrypted data with a second encryption key and a copy destination physical address indicative of the second physical storage location.
    Type: Application
    Filed: January 21, 2021
    Publication date: June 3, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi KANNO
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11023371
    Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • STORAGE DEVICE AND STORAGE SYSTEM
    Publication number: 20210149568
    Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 20, 2021
    Applicant: Kioxia Corporation
    Inventors: Yasuhito YOSHIMIZU, Takashi FUKUSHIMA, Tatsuro HITOMI, Arata INOUE, Masayuki MIURA, Shinichi KANNO, Toshio FUJISAWA, Keisuke NAKATSUKA, Tomoya SANUKI
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210149797
    Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.
    Type: Application
    Filed: September 10, 2020
    Publication date: May 20, 2021
    Applicant: Kioxia Corporation
    Inventors: Shinichi Kanno, Naoki Esaka
  • Memory system and method for controlling nonvolatile memory in which write data are stored in a shared device side write buffer shared by a plurality of write destination blocks
    Patent number: 11003385
    Abstract: According to one embodiment, a memory system stores write data received from a host to a shared write buffer for write destination blocks, acquires first write data for plural pages from the shared write buffer, and writes the first write data to a first write destination block by a first-step write operation. When receiving write data from the host in a state in which an empty region does not exist in the shared write buffer, the memory system discards write data in the shared write buffer in which the first-step write operation has been finished. In a case where the first write data do not exist in the shared write buffer when a second-step write operation of the first write data is to be executed, the memory system transmits a request to acquire the first write data to the host.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 11, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • NONVOLATILE MEMORY SYSTEM AND METHOD FOR CONTROLLING WRITE AND READ OPERATIONS IN THE NONVOLATILE MEMORY BY A HOST
    Publication number: 20210124531
    Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.
    Type: Application
    Filed: January 8, 2021
    Publication date: April 29, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi KANNO
  • STORAGE DEVICE THAT SECURES A BLOCK FOR A STREAM OR NAMESPACE AND SYSTEM HAVING THE STORAGE DEVICE
    Publication number: 20210117092
    Abstract: A storage device includes a nonvolatile semiconductor memory device including a plurality of physical blocks and a memory controller. The memory controller is configured to associate one or more physical blocks to each of a plurality of stream IDs, execute a first command containing a first stream ID received from a host, by storing write data included in the write IO in the one or more physical blocks associated with the first stream ID, and execute a second command containing a second stream ID received from the host, by selecting a first physical block that includes valid data and invalid data, transfer the valid data stored in the first physical block to a second physical block, and associate the first physical block from which the valid data has been transferred, with the second stream ID.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Inventors: Daisuke HASHIMOTO, Shinichi KANNO
  • Memory system that constructs virtual storage regions for virtual machines
    Patent number: 10983701
    Abstract: A memory system connectable to a host includes a nonvolatile memory and a controller. The controller is configured to generate one or more virtual storage regions each of which is associated with a virtual machine running in the host, using physical memory regions of the nonvolatile memory, maintain a threshold value for each of said one or more virtual storage regions, determine a cumulative amount of data that have been written in each of said one or more virtual storage regions, and restrict writing of data with respect to a virtual storage region for which the cumulative amount exceeds the threshold value.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • MEMORY DEVICE AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM
    Publication number: 20210109854
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210081327
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a movement request from a host, the movement request designating a logical address of movement target data. When update data corresponding to the designated logical address is not written to the nonvolatile memory by a write request from the host in a period from the reception of the movement request to start of movement of data corresponding to the designated logical address, the controller executes a movement process of moving data corresponding to the designated logical address to a movement destination block in the nonvolatile memory. When the update data is written to the nonvolatile memory in the period, the controller does not execute the movement process.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventors: Kensaku YAMAGUCHI, Shinichi KANNO
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210064290
    Abstract: According to one embodiment, a memory system determines, for each of groups corresponding to streams, whether or not a length of write data associated with a set of write commands belonging to a same group reaches a minimum write size of a nonvolatile memory. When a length of write data associated with a set of write commands belonging to a first group corresponding to a first stream reaches the minimum write size, the memory system transfers the write data associated with the set of write commands belonging to the first group from a write buffer in a memory of the host to a first buffer in the memory system, and writes the write data transferred to the first buffer to a first write destination block corresponding to the first stream.
    Type: Application
    Filed: March 11, 2020
    Publication date: March 4, 2021
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210064291
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller prohibits processing for transitioning a state of a block associated with an uncompleted read command to a state reusable as a new write destination block, on the basis of a plurality of first counter values corresponding to a plurality of blocks in the nonvolatile memory. The controller prohibits release of a region in a buffer that stores data being written or waiting for being written to a write destination block associated with an uncompleted read command, on the basis of a plurality of second counter values corresponding to a plurality of write destination blocks.
    Type: Application
    Filed: March 11, 2020
    Publication date: March 4, 2021
    Applicant: Kioxia Corporation
    Inventor: Shinichi Kanno
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210064289
    Abstract: According to one embodiment, a memory system checks a first total size indicative of a sum of data lengths specified by first write commands stored in a first submission queue of a host corresponding to a first stream. When the first total size is greater than or equal to a minimum write size, the memory system fetches a set of first write commands stored in the first submission queue, transfers first write data associated with the set of first write commands from a memory of the host to the memory system, and writes the first write data into a first write destination block allocated for the first stream.
    Type: Application
    Filed: March 11, 2020
    Publication date: March 4, 2021
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210064288
    Abstract: According to one embodiment, a memory system writes first write data into each non-defective physical block belonging to a first write destination block group. The memory system notifies a host of a first identifier of the first write data, an address specifying the first write destination block group, a first offset indicating a top write destination physical storage location in the first write destination block group in which the first write data is written, length of the first write data, and first bitmap information including a plurality of bits, each of the bits corresponding to each of physical blocks belonging to the first write destination block group and indicating whether or not the corresponding physical block is a defective block.
    Type: Application
    Filed: March 11, 2020
    Publication date: March 4, 2021
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Takehiko KURASHIGE