Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system and method of controlling nonvolatile memory with checking a total size indicative of a sum of data length specified by a write command
    Patent number: 11163493
    Abstract: According to one embodiment, a memory system checks a first total size indicative of a sum of data lengths specified by first write commands stored in a first submission queue of a host corresponding to a first stream. When the first total size is greater than or equal to a minimum write size, the memory system fetches a set of first write commands stored in the first submission queue, transfers first write data associated with the set of first write commands from a memory of the host to the memory system, and writes the first write data into a first write destination block allocated for the first stream.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 2, 2021
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • INFORMATION PROCESSING DEVICE, NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM, AND INFORMATION PROCESSING SYSTEM
    Publication number: 20210334207
    Abstract: According to one embodiment, an information processing device includes a nonvolatile memory, assignment unit, and transmission unit. The assignment unit assigns logical address spaces to spaces. Each of the spaces is assigned to at least one write management area included in a nonvolatile memory. The write management area is a unit of an area which manages the number of write. The transmission unit transmits a command for the nonvolatile memory and identification data of a space assigned to a logical address space corresponding to the command.
    Type: Application
    Filed: July 9, 2021
    Publication date: October 28, 2021
    Inventors: Shinichi Kanno, Daisuke Hashimoto
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11150835
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: October 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Computing system and method for controlling storage device
    Patent number: 11151029
    Abstract: According to one embodiment, a computing system transmits to a storage device a write request designating a first logical address for identifying first data to be written and a length of the first data. The computing system receives from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block by the storage device, and a first physical storage location in the first block to which the first data is written. The computing system updates a first table which manages mapping between logical addresses and physical addresses of the storage device and maps the first physical address to the first logical address.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 19, 2021
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11144451
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11132295
    Abstract: According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies a set of data included in a copy-source block for garbage collection and corresponding respectively to reference counts belonging to a first reference count range to a first copy-destination block, and copies a set of data included in the copy-source block and corresponding respectively to reference counts belonging to a second reference count range having a lower limit higher than an upper limit of the first reference count range to a second copy-destination block.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: September 28, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Naoki Esaka
  • Memory system and method of controlling nonvolatile memory by controlling the writing of data to and reading of data from a plurality of blocks in the nonvalatile memory
    Patent number: 11119701
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller prohibits processing for transitioning a state of a block associated with an uncompleted read command to a state reusable as a new write destination block, on the basis of a plurality of first counter values corresponding to a plurality of blocks in the nonvolatile memory. The controller prohibits release of a region in a buffer that stores data being written or waiting for being written to a write destination block associated with an uncompleted read command, on the basis of a plurality of second counter values corresponding to a plurality of write destination blocks.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: September 14, 2021
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • STORAGE DEVICE, STORAGE SYSTEM, AND METHOD
    Publication number: 20210278972
    Abstract: According to one embodiment, a storage device includes a non-volatile memory and a control unit that is electrically connected to the non-volatile memory and that is configured to control the non-volatile memory. The control unit is configured to manage a plurality of management areas obtained by logically partitioning storage area of the non-volatile memory, when a write request is received that includes data for which a valid term has been set, determine, based on the valid term, a first management area from among the management areas, write the data included in the write request to the determined first management area, and when the data written to the first management area is erased, collectively erase all data written in the first management area which includes the data.
    Type: Application
    Filed: December 11, 2020
    Publication date: September 9, 2021
    Applicant: Kioxia Corporation
    Inventors: Takeshi ISHIHARA, Yohei HASEGAWA, Shinichi KANNO, Kohei OKUDA, Masataka GOTO
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210278974
    Abstract: According to one embodiment, a memory system manages wear of each of a plurality of blocks in a nonvolatile memory. The memory system receives, from a host, a write request including a parameter specifying a data retention term required for first data to be written. The memory system selects, from the blocks, a first block in which a data retention term estimated from the wear of the first block is longer than or equal to the specified data retention term. The memory system writes the first data to the first block.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 9, 2021
    Inventors: Shinichi Kanno, Hideki Yoshida
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210279001
    Abstract: According to one embodiment, a memory system manages a plurality of first weights that correspond to the plurality of queues, and a plurality of second weights that correspond to the plurality of queues. The memory system selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority, and starts execution of a command stored in the selected queue. The memory system updates the second weight corresponding to the selected queue by subtracting the first weight corresponding to the selected queue from the second weight corresponding to the selected queue or by adding the first weight corresponding to the selected queue to the second weight corresponding to the selected queue.
    Type: Application
    Filed: September 10, 2020
    Publication date: September 9, 2021
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME
    Publication number: 20210266014
    Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
    Type: Application
    Filed: May 11, 2021
    Publication date: August 26, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi KANNO, Hironori UCHIKAWA
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210255803
    Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.
    Type: Application
    Filed: September 11, 2020
    Publication date: August 19, 2021
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • Memory system and method for controlling nonvolatile memory
    Patent number: 11093137
    Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 17, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210248065
    Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
    Type: Application
    Filed: April 27, 2021
    Publication date: August 12, 2021
    Inventor: Shinichi Kanno
  • Information processing device, non-transitory computer readable recording medium, and information processing system
    Patent number: 11086775
    Abstract: According to one embodiment, an information processing device includes a nonvolatile memory, assignment unit, and transmission unit. The assignment unit assigns logical address spaces to spaces. Each of the spaces is assigned to at least one write management area included in a nonvolatile memory. The write management area is a unit of an area which manages the number of write. The transmission unit transmits a command for the nonvolatile memory and identification data of a space assigned to a logical address space corresponding to the command.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 10, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Daisuke Hashimoto
  • Memory system and method for controlling nonvolatile memory by a host
    Patent number: 11074015
    Abstract: According to one embodiment, a memory system receives from a host read commands each designating both of a block address of a read target block and a read target storage location in the read target block, and executes a data read operation in accordance with each of the received read commands. In response to receiving from the host a first command to transition a first block to which data is already written to a reusable state of being reusable as a new write destination block, the memory system determine whether an incomplete read command designating a block address of the first block exists or not. In a case where the incomplete read command exists, the memory system executes the first command after execution of the incomplete read command is completed.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: July 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Memory system and method of controlling nonvolatile memory
    Patent number: 11074178
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a movement request from a host, the movement request designating a logical address of movement target data. When update data corresponding to the designated logical address is not written to the nonvolatile memory by a write request from the host in a period from the reception of the movement request to start of movement of data corresponding to the designated logical address, the controller executes a movement process of moving data corresponding to the designated logical address to a movement destination block in the nonvolatile memory. When the update data is written to the nonvolatile memory in the period, the controller does not execute the movement process.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 27, 2021
    Assignee: Kioxia Corporation
    Inventors: Kensaku Yamaguchi, Shinichi Kanno
  • MEMORY SYSTEM CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210223962
    Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.
    Type: Application
    Filed: September 14, 2020
    Publication date: July 22, 2021
    Applicant: Kioxia Corporation
    Inventors: Naoki ESAKA, Shinichi KANNO
  • MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210223994
    Abstract: According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.
    Type: Application
    Filed: September 10, 2020
    Publication date: July 22, 2021
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Koichi NAGAI
  • MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    Publication number: 20210223986
    Abstract: According to one embodiment, a memory system stores write data received from a host to a shared write buffer for write destination blocks, acquires first write data for plural pages from the shared write buffer, and writes the first write data to a first write destination block by a first-step write operation. When receiving write data from the host in a state in which an empty region does not exist in the shared write buffer, the memory system discards write data in the shared write buffer in which the first-step write operation has been finished. In a case where the first write data do not exist in the shared write buffer when a second-step write operation of the first write data is to be executed, the memory system transmits a request to acquire the first write data to the host.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Applicant: Toshiba Memory Corporation
    Inventor: Shinichi KANNO