Patents by Inventor Shinichi Takagi
Shinichi Takagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11227953Abstract: A tunneling field effect transistor according to an embodiment of the present invention includes: a first semiconductor layer having a first conductive type; a second semiconductor layer having a second conductive type and realizing a heterojunction with respect to the first semiconductor layer in a first region; a gate insulating layer over the second semiconductor layer in the first region; a gate electrode layer over the gate insulating layer; a first electrode layer electrically connected to the first semiconductor layer; a second electrode layer electrically connected to the second semiconductor layer; and a first insulating layer interposed between the first semiconductor layer and the second semiconductor layer in a second region adjacent to the first region toward the second electrode layer.Type: GrantFiled: November 28, 2018Date of Patent: January 18, 2022Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Kimihiko Kato, Shinichi Takagi, Mitsuru Takenaka, Hitoshi Tabata, Hiroaki Matsui
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Patent number: 11199663Abstract: A plurality of bandpass filters (2) are arranged side by side in a row on a fixed surface (1a) of a glass block (1) and fixed using an adhesive (3). Each bandpass filter (2) includes a coating film (6) for transmitting or reflecting light depending on a wavelength. Each bandpass filter (2) includes a first surface (2a) fixed to the fixed surface (1a), and a second surface (2b) opposite to the first surface (2a) and having a width larger than that of the first surface (2a). Opposing side surfaces of the adjacent bandpass filters (2) include a first portion (2c) on the first surface (2a) side and a second portion (2d) on the second surface (2b) side. A spacing between the first portions (2c) of the adjacent bandpass filters (2) is wider than a spacing between the second portions (2d) of the adjacent bandpass filters (2).Type: GrantFiled: April 5, 2018Date of Patent: December 14, 2021Assignee: Mitsubishi Electric CorporationInventors: Toshiharu Kato, Shinichi Takagi
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Publication number: 20210173148Abstract: A plurality of bandpass filters (2) are arranged side by side in a row on a fixed surface (1a) of a glass block (1) and fixed using an adhesive (3). Each bandpass filter (2) includes a coating film (6) for transmitting or reflecting light depending on a wavelength. Each bandpass filter (2) includes a first surface (2a) fixed to the fixed surface (1a), and a second surface (2b) opposite to the first surface (2a) and having a width larger than that of the first surface (2a). Opposing side surfaces of the adjacent bandpass filters (2) include a first portion (2c) on the first surface (2a) side and a second portion (2d) on the second surface (2b) side. A spacing between the first portions (2c) of the adjacent bandpass filters (2) is wider than a spacing between the second portions (2d) of the adjacent bandpass filters (2).Type: ApplicationFiled: April 5, 2018Publication date: June 10, 2021Applicant: Mitsubishi Electric CorporationInventors: Toshiharu KATO, Shinichi TAKAGI
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Patent number: 10983411Abstract: A MOS optical modulator having high modulation efficiency and a method of manufacturing the same are provided. A MOS optical modulator includes: a p-type Si layer constituting an optical waveguide; a gate insulating film provided on the optical waveguide; a gate layer provided on the gate insulating film and formed of an n-type group III-V semiconductor; a first contact portion connected to the gate layer; and a second contact portion connected to the Si layer.Type: GrantFiled: August 17, 2017Date of Patent: April 20, 2021Assignee: THE UNIVERSITY OF TOKYOInventors: Mitsuru Takenaka, Jae-Hoon Han, Shinichi Takagi
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Publication number: 20210005758Abstract: A tunneling field effect transistor according to an embodiment of the present invention includes: a first semiconductor layer having a first conductive type; a second semiconductor layer having a second conductive type and realizing a heterojunction with respect to the first semiconductor layer in a first region; a gate insulating layer over the second semiconductor layer in the first region; a gate electrode layer over the gate insulating layer; a first electrode layer electrically connected to the first semiconductor layer; a second electrode layer electrically connected to the second semiconductor layer; and a first insulating layer interposed between the first semiconductor layer and the second semiconductor layer in a second region adjacent to the first region toward the second electrode layer.Type: ApplicationFiled: November 28, 2018Publication date: January 7, 2021Inventors: Kimihiko KATO, Shinichi TAKAGI, Mitsuru TAKENAKA, Hitoshi TABATA, Hiroaki MATSUI
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Publication number: 20190285964Abstract: A MOS optical modulator having high modulation efficiency and a method of manufacturing the same are provided. A MOS optical modulator includes: a p-type Si layer constituting an optical waveguide; a gate insulating film provided on the optical waveguide; a gate layer provided on the gate insulating film and formed of an n-type group III-V semiconductor; a first contact portion connected to the gate layer; and a second contact portion connected to the Si layer.Type: ApplicationFiled: August 17, 2017Publication date: September 19, 2019Inventors: MITSURU TAKENAKA, JAE-HOON HAN, SHINICHI TAKAGI
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Patent number: 9117658Abstract: There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer.Type: GrantFiled: August 23, 2013Date of Patent: August 25, 2015Assignees: SUMITOMO CHEMICAL COMPANY, LIMITED, THE UNIVERSITY OF TOKYOInventors: Mitsuru Takenaka, Shinichi Takagi, Jaehoon Han, Tomoyuki Takada, Takenori Osada, Masahiko Hata
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Patent number: 9112035Abstract: A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.Type: GrantFiled: March 2, 2012Date of Patent: August 18, 2015Assignees: SUMITOMO CHEMICAL COMPANY, LIMITED, THE UNIVERSITY OF TOKYO, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Hisashi Yamada, Masahiko Hata, Masafumi Yokoyama, Mitsuru Takenaka, Shinichi Takagi, Tetsuji Yasuda, Hideki Takagi, Yuji Urabe
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Patent number: 8901656Abstract: Provided is a semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity Ea1 of the first crystal layer is larger than the electron affinity Ea2 of the second crystal layer.Type: GrantFiled: August 30, 2013Date of Patent: December 2, 2014Assignees: Sumitomo Chemical Company, Limited, The University of Tokyo, National Institute of Advanced Industrial Science and TechnologyInventors: Takeshi Aoki, Hisashi Yamada, Noboru Fukuhara, Masahiko Hata, Masafumi Yokoyama, SangHyeon Kim, Mitsuru Takenaka, Shinichi Takagi, Tetsuji Yasuda
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Patent number: 8779471Abstract: Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1?1, 0?y1?1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0?x2?1, 0?y2?1, y2?y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer.Type: GrantFiled: March 6, 2012Date of Patent: July 15, 2014Assignees: Sumitomo Chemical Company, Limited, The University of Tokyo, National Institute of Advanced Industrial Science and TechnologyInventors: Masahiko Hata, Hisashi Yamada, Noboru Fukuhara, Shinichi Takagi, Mitsuru Takenaka, Masafumi Yokoyama, Tetsuji Yasuda, Yuji Urabe, Noriyuki Miyata, Taro Itatani, Hiroyuki Ishii
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Publication number: 20140091393Abstract: There is provided a semiconductor device including: a first source and a first drain of a first-channel-type MISFET formed on a first semiconductor crystal layer, which are made of a compound having an atom constituting the first semiconductor crystal layer and a nickel atom, a compound having an atom constituting the first semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the first semiconductor crystal layer, a nickel atom, and a cobalt atom; and a second source and a second drain of a second-channel-type MISFET formed on a second semiconductor crystal layer, which are made of a compound having an atom constituting the second semiconductor crystal layer and a nickel atom, a compound having an atom constituting the second semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the second semiconductor crystal layer, a nickel atom, and a cobalt atom.Type: ApplicationFiled: December 6, 2013Publication date: April 3, 2014Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, THE UNIVERSTIY OF TOKYOInventors: Masahiko HATA, Hisashi YAMADA, Masafumi YOKOYAMA, SangHyeon Kim, Mitsuru TAKENAKA, Shinichi TAKAGI, Tetsuji YASUDA
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Publication number: 20140091392Abstract: There is provided a semiconductor device including a first channel-type first MISFET formed and a second channel-type second MISFET: a first source and a first drain of the first MISFET and a second source and a second drain of the second MISFET are made of the same conductive substance, and the work function ?M of the conductive substance satisfies at least one of relations respectively represented by (1) ?1<?M<?2+Eg2, and (2) |?M??1|?0.1 eV and |(?2+Eg2)??M|?0.1 eV, where ?1 represents an electron affinity of an N-type semiconductor crystal layer, and ?2 and Eg2 represent an electron affinity and a band gap of a crystal of a P-type semiconductor crystal layer.Type: ApplicationFiled: December 6, 2013Publication date: April 3, 2014Applicants: Sumitomo Chemical Company, Limited, National Institute of Advanced Industrial Science And Technology, The University of TokyoInventors: Tomoyuki TAKADA, Hisashi YAMADA, Masahiko HATA, Shinichi TAKAGI, Tatsuro MAEDA, Yuji URABE, Tetsuji YASUDA
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Publication number: 20140091398Abstract: Provided is a semiconductor device including a first source and a first drain of a P-channel-type MISFET formed on a Ge wafer, which are made of a compound having a Ge atom and a nickel atom, a compound having a Ge atom and a cobalt atom, or a compound having a Ge atom, a nickel atom, and a cobalt atom, and a second source and a second drain of an N-channel-type MISFET formed on the Group III-V compound semiconductor, which are made of a compound having a Group III atom, a Group V atom, and a nickel atom, a compound having a Group III atom, a Group V atom, and a cobalt atom, or a compound having a Group III atom, a Group V atom, a nickel atom, and a cobalt atom.Type: ApplicationFiled: December 6, 2013Publication date: April 3, 2014Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, THE UNIVERSITY OF TOKYOInventors: Masahiko HATA, Hisashi YAMADA, Masafumi YOKOYAMA, SangHyeon Kim, Rui ZHANG, Mitsuru TAKENAKA, Shinichi TAKAGI, Tetsuji YASUDA
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Publication number: 20140054726Abstract: There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer.Type: ApplicationFiled: August 23, 2013Publication date: February 27, 2014Applicants: THE UNIVERSITY OF TOKYO, SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Mitsuru TAKENAKA, Shinichi TAKAGI, Jaehoon HAN, Tomoyuki TAKADA, Takenori OSADA, Masahiko HATA
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Publication number: 20130341721Abstract: Provided is a semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity Ea1 of the first crystal layer is larger than the electron affinity Ea2 of the second crystal layer.Type: ApplicationFiled: August 30, 2013Publication date: December 26, 2013Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, THE UNIVERSITY OF TOKYOInventors: Takeshi AOKI, Hisashi YAMADA, Noboru FUKUHARA, Masahiko HATA, Masafumi YOKOYAMA, SangHyeon KIM, Mitsuru TAKENAKA, Shinichi TAKAGI, Tetsuji YASUDA
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Patent number: 8518543Abstract: A sliding member is produced by forming hardening layers with two-layered structure on surface of a substrate metal with a Vickers hardness of not more than Hv300, such as aluminum or magnesium alloy for example, and then forming a DLC film having surface roughness defined as maximum height roughness Rz of 1 to 10 ?m further on the hardening layers. The above-described hardening layers are composed of a first hardening layer dispersed with heavy metal particles, preferably made of tungsten and/or tantalum in the substrate metal, and a second hardening layer formed under the first hardening layer.Type: GrantFiled: February 3, 2009Date of Patent: August 27, 2013Assignees: FujiWPC Co., Ltd., Fuji Kihan Co., Ltd.Inventors: Makoto Kano, Takahiro Horiuchi, Shinichi Takagi, Masao Kumagai, Eiji Shimodaira, Yoshio Miyasaka
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Patent number: 8431459Abstract: It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method. Provided is a semiconductor wafer comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer.Type: GrantFiled: March 26, 2009Date of Patent: April 30, 2013Assignee: The University of TokyoInventors: Mitsuru Takenaka, Shinichi Takagi, Masahiko Hata, Osamu Ichikawa
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Publication number: 20120228673Abstract: Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1?1, 0?y1?1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0?x2?1, 0?y2?1, y2?y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer.Type: ApplicationFiled: March 6, 2012Publication date: September 13, 2012Applicants: SUMITOMO CHEMICAL COMPANY, National Institute of Advanced Industrial Science and Technology, The University of TokyoInventors: Masahiko HATA, Hisashi Yamada, Noboru Fukuhara, Shinichi Takagi, Mitsuru Takenaka, Masafumi Yokoyama, Tetsuji Yasuda, Yuji Urabe, Noriyuki Miyata, Taro Itatani, Hiroyuki Ishii
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Publication number: 20120205747Abstract: A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.Type: ApplicationFiled: March 2, 2012Publication date: August 16, 2012Applicants: THE UNIVERSITY OF TOKYO, SUMITOMO CHEMICAL CO., LTD.Inventors: Hisashi YAMADA, Masahiko HATA, Masafumi YOKOYAMA, Mitsuru TAKENAKA, Shinichi TAKAGI, Tetsuji YASUDA, Hideki TAKAGI, Yuji URABE
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Patent number: 8174095Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.Type: GrantFiled: February 28, 2011Date of Patent: May 8, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Toshifumi Irisawa, Shinichi Takagi, Naoharu Sugiyama