Patents by Inventor Shinichi Takagi

Shinichi Takagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110233689
    Abstract: There is provided a semiconductor device that includes a III-V Group compound semiconductor having a zinc-blende-type crystal structure, an insulating material being in contact with the (111) plane of the III-V Group compound semiconductor, a plane of the III-V Group compound semiconductor equivalent to the (111) plane, or a plane that has an off angle with respect to the (111) plane or the plane equivalent to the (111) plane, and an MIS-type electrode being in contact with the insulating material and including a metal conductive material.
    Type: Application
    Filed: November 27, 2009
    Publication date: September 29, 2011
    Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, THE UNIVERSITY OF TOKYO, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Masahiko Hata, Noboru Fukuhara, Hisashi Yamada, Shinichi Takagi, Masakazu Sugiyama, Mitsuru Takenaka, Tetsuji Yasuda, Noriyuki Miyata, Taro Itatani, Hiroyuki Ishii, Akihiro Ohtake, Jun Nara
  • Patent number: 8008751
    Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshifumi Irisawa, Shinichi Takagi, Naoharu Sugiyama
  • Publication number: 20110147805
    Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.
    Type: Application
    Filed: February 28, 2011
    Publication date: June 23, 2011
    Inventors: Toshifumi Irisawa, Shinichi Takagi, Naoharu Sugiyama
  • Publication number: 20110044572
    Abstract: A sliding member is produced by forming hardening layers with two-layered structure on surface of a substrate metal with a Vickers hardness of not more than Hv300, such as aluminum or magnesium alloy for example, and then forming a DLC film having surface roughness defined as maximum height roughness Rz of 1 to 10 ?m further on the hardening layers. The above-described hardening layers are composed of a first hardening layer dispersed with heavy metal particles, preferably made of tungsten and/or tantalum in the substrate metal, and a second hardening layer formed under the first hardening layer.
    Type: Application
    Filed: February 3, 2009
    Publication date: February 24, 2011
    Applicant: FUJIWPC CO., LTD.
    Inventors: Makoto Kano, Takahiro Horiuchi, Shinichi Takagi, Masao Kumagai, Eiji Shimodaira, Yoshio Miyasaka
  • Publication number: 20110018033
    Abstract: It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method. Provided is a semiconductor wafer comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer.
    Type: Application
    Filed: March 26, 2009
    Publication date: January 27, 2011
    Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Mitsuru Takenaka, Shinichi Takagi, Masahiko Hata, Osamu Ichikawa
  • Patent number: 7679181
    Abstract: A semiconductor device includes: a package case in which a semiconductor element is mounted, the package case having a bonding portion; a cap having a bonding portion bonded to the bonding portion of the package case so as to hermetically seal the semiconductor element; and one or more bonding/sealing wires disposed between and in contact with the bonding portion of the package case and the bonding portion of the cap such that the one or more bonding/sealing wires form a closed loop and hermetically seal the semiconductor element.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: March 16, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Junji Fujino, Shinichi Takagi
  • Patent number: 7659537
    Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y?0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: February 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Tezuka, Shinichi Takagi, Tomohisa Mizuno
  • Patent number: 7622773
    Abstract: In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: November 24, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshifumi Irisawa, Toshinori Numata, Shinichi Takagi, Naoharu Sugiyama
  • Patent number: 7619239
    Abstract: A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: November 17, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshifumi Irisawa, Toshinori Numata, Tsutomu Tezuka, Naoharu Sugiyama, Shinichi Takagi
  • Patent number: 7557018
    Abstract: A substrate used for fabricating devices thereon includes an insulating film, and a monocrystal Ge thin layer formed on the insulating film in contact therewith, the monocrystal Ge thin layer having a thickness not more than 6 nm. The monocrystal Ge thin layer has a thickness not less than 2 nm and a compressive strain.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: July 7, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shu Nakaharai, Tsutomu Tezuka, Shinichi Takagi
  • Patent number: 7507634
    Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: March 24, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Mie Matsuo, Ichiro Mizushima, Yoshitaka Tsunashima, Shinichi Takagi
  • Patent number: 7489042
    Abstract: A stem for an optical element includes a base-like portion located on a portion of a package side surface of an eyelet, higher than the package side surface. A block is located on a surface of the base-like portion of the eyelet. An optical element mounting surface of the block projects outward, overhanging a side face of the base-like portion, close to lead electrodes which are inserted through holes of the eyelet, respectively, and sealed with sealing glass. High-frequency line substrates are located on the optical element mounting surface of the block, and Au films of the high-frequency line substrate are electrically connected to respective lead electrodes.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: February 10, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Isao Oshima, Shinichi Takagi
  • Publication number: 20090020866
    Abstract: A semiconductor device includes: a package case in which a semiconductor element is mounted, the package case having a bonding portion; a cap having a bonding portion bonded to the bonding portion of the package case so as to hermetically seal the semiconductor element; and one or more bonding/sealing wires disposed between and in contact with the bonding portion of the package case and the bonding portion of the cap such that the one or more bonding/sealing wires form a closed loop and hermetically seal the semiconductor element.
    Type: Application
    Filed: October 31, 2007
    Publication date: January 22, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji Fujino, Shinichi Takagi
  • Publication number: 20080135886
    Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.
    Type: Application
    Filed: December 5, 2007
    Publication date: June 12, 2008
    Inventors: Toshifumi Irisawa, Shinichi Takagi, Naoharu Sugiyama
  • Publication number: 20080003771
    Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
    Type: Application
    Filed: June 19, 2007
    Publication date: January 3, 2008
    Inventors: Tsutomu Sato, Mie Matsuo, Ichiro Mizushima, Yoshitaka Tsunashima, Shinichi Takagi
  • Patent number: 7313292
    Abstract: An optical component comprises an optical transmission element (e.g., an optical lens) whose circumferential wall partially joins a metal holder via a joining material (e.g., a low melting point glass), wherein stress is normally applied to the optical transmission element in a compression direction when joining the metal holder. The optical transmission element is inserted into a through hole of the metal holder, and the joining material is kept in a bank actualized by a tapered portion formed in proximity to one end of the through hole of the metal holder. This prevents tensile stress from being applied to the optical transmission element; thus, it is possible to avoid the occurrence of cracks and separations in the optical transmission element; and it is possible to avoid the occurrence of errors in optical characteristics, regardless of variations of the environmental temperature, so that, the optical component is improved in reliability.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: December 25, 2007
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Yamaha Corporation
    Inventors: Yoshihiro Hashimoto, Ken Matsuoka, Shinichi Takagi, Katsunori Suzuki, Tetsutsugu Hamano
  • Patent number: 7301974
    Abstract: An optical signal emitted from a semiconductor laser is converged by a lens and then received by a single uniaxial birefringent crystal having a C axis that is inclined at an angle other than 90 degrees against a laser optical axis to output an optical signal having a polarized wave component of constant intensity corresponding to the wavelength of the optical signal regardless of temperature changes. The optical signal has an ordinary ray vibrating in a direction perpendicular to a plane including both the C axis and the laser optical axis, and an extraordinary ray vibrating in a direction perpendicular to both the ordinary ray and the laser optical axis. A first main photo detector detects the intensity of a p-polarized component of the optical signal that has passed through a polarizer and a second photo detector directly receives the optical signal converged by the lens.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: November 27, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masao Imaki, Yoshihito Hirano, Makoto Satou, Kenji Masuda, Akihiro Adachi, Shinichi Takagi, Yasunori Nishimura
  • Publication number: 20070241399
    Abstract: In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.
    Type: Application
    Filed: February 13, 2007
    Publication date: October 18, 2007
    Inventors: Toshifumi Irisawa, Toshinori Numata, Shinichi Takagi, Naoharu Sugiyama
  • Patent number: 7283302
    Abstract: A wavelength filter includes a solid material that is optically transparent and including a pair of planar surfaces substantially parallel to each other; and a supporting member that supports the solid material on a planar surface of the solid material other than the pair of planar surfaces, the supporting member having a rigidity higher than that of the solid material. The solid material is a birefringent material of which an optical axis makes a predetermined angle with respect to a normal to the pair of planar surfaces, and the wavelength filter selects light having a wavelength that is determined by an optical length between the pair of planar surfaces by resonating the light between the pair of planar surfaces.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: October 16, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masao Imaki, Yoshihito Hirano, Makoto Sato, Akihiro Adachi, Shinichi Takagi, Yasunori Nisimura
  • Patent number: 7235456
    Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: June 26, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Mie Matsuo, Ichiro Mizushima, Yoshitaka Tsunashima, Shinichi Takagi