Patents by Inventor Shinichiro Hayashi

Shinichiro Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6358758
    Abstract: A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75° C., and after 109 negative polarization switching pulses at 125° C.
    Type: Grant
    Filed: May 19, 2001
    Date of Patent: March 19, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Shinichiro Hayashi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Patent number: 6355619
    Abstract: Disclosed are peptide-based compositions and methods for inhibiting and modulating the actions of CXC intercrine molecules. The antileukinate peptides described inhibit IL-8, GRO and MIP2&bgr; binding to neutrophils and neutrophil activation. The peptides are particularly advantageous as they inhibit IL-8-induced enzyme release at a 25 fold lower concentration than is required to inhibit chemotaxis, which makes them ideal for treating various inflammatory diseases and disorders including, amongst others, Adult Respiratory Distress Syndrome (ARDS), cystic fibrosis and chronic bronchitis. The invention further includes methods for inhibiting tumor cell growth by employing selected members of the disclosed group of peptides to inhibit a-chemokine binding to the tumor cell.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: March 12, 2002
    Assignee: Board of Regents, The University of Texas System
    Inventors: Edmund J. Miller, Shinichiro Hayashi
  • Patent number: 6351004
    Abstract: A tunneling transistor is provided as an effective means for miniaturization of a semiconductor integrated circuit having nonvolatile memory. An insulating layer is disposed on a silicon substrate. A source and a drain are disposed on the insulating layer, with an insulator of a few nanometers in thickness that provides a tunnel barrier being interposed between the source and the drain. A ferroelectric layer that exhibits spontaneous polarization is disposed directly above a region of the source that is adjacent to the insulator. With this construction, when the ferroelectric layer is polarized in a predetermined direction, at least a portion of the region of the source adjacent to the insulator forms a depletion region, with it being possible to vary the amount of current tunneling through the insulator depending on whether the ferroelectric layer is polarized or not.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: February 26, 2002
    Assignee: Matsushita Electric Ind. Co., Ltd.
    Inventors: Yasuhiro Shimada, Shinichiro Hayashi, Kiyoshi Uchiyama, Keisuke Tanaka
  • Publication number: 20020000600
    Abstract: A semiconductor memory includes plural lower electrodes formed on a semiconductor substrate; a capacitor dielectric film of an insulating metal oxide continuously formed over the plural lower electrodes; plural upper electrodes formed on the capacitor dielectric film in positions respectively corresponding to the plural lower electrodes; and plural transistors formed on the semiconductor substrate. The plural lower electrodes are respectively connected with source regions of the plural transistors.
    Type: Application
    Filed: June 23, 1999
    Publication date: January 3, 2002
    Inventors: YOSHIHISA NAGANO, SHINICHIRO HAYASHI, YASUHIRO UEMOTO
  • Patent number: 6320604
    Abstract: A multi power type thermal head which has a heating element for producing heat with different energies, an added resistor being connected to the heating element, first switch element for controlling the heating element in an operation state or a nonoperational state, and second switch element for controlling the heating element and the added resistor in an operation state or a nonoperational state. To control the thermal head in a first energy state, heating the heating element is controlled by the first switching element. To control the thermal head in a second energy state, the heating element and the added resistor are controlled by the second switching element with the heating element and the added resistor connected in series.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: November 20, 2001
    Assignee: TDK Corporation
    Inventors: Bunji Moriya, Shinichiro Hayashi, Kazuhito Uchida
  • Publication number: 20010041372
    Abstract: A method for forming an interface insulator layer in a ferroelectric FET memory, in which a liquid precursor is applied to a semiconductor substrate. Preferably, the liquid precursor is an enhanced metalorganic decomposition (“EMOD”) precursor, applied using a liquid-source misted deposition technique. Preferably, the EMOD precursor solution applied to the substrate contains metal ethylhexanoates containing metal moieties in relative molar proportions for forming an interface insulator layer containing ZrO2, CeO2, Y2O3 or (Ce1−xZrx)O2, wherein 0≦x≦1.
    Type: Application
    Filed: March 29, 2001
    Publication date: November 15, 2001
    Applicant: Symetrix Corporation
    Inventors: Koji Arita, Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
  • Publication number: 20010041373
    Abstract: A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by carefully controlled drying, soft baking, and annealing conditions.
    Type: Application
    Filed: April 26, 2001
    Publication date: November 15, 2001
    Applicant: Matsushita Electronics Corporation
    Inventors: Shinichiro Hayashi, Tatsuo Otsuki
  • Publication number: 20010031505
    Abstract: A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75° C., and after 109 negative polarization switching pulses at 125° C.
    Type: Application
    Filed: May 19, 2001
    Publication date: October 18, 2001
    Applicant: Symetrix Corporation and Matsushita Electronics Corporation
    Inventors: Koji Arita, Shinichiro Hayashi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Publication number: 20010028074
    Abstract: A capacitor including a capacitor lower electrode, a capacitor dielectric film of a highly dielectric film or a ferroelectric film and a capacitor upper electrode is formed on a semiconductor substrate. A protection film is formed on the semiconductor substrate so as to cover the capacitor. A first TEOS film having a relatively large water content is formed on the protection film through first TEOS-O3 CVD where an ozone concentration is relatively low. A second TEOS-O3 film having a relatively small water content is formed on the first TEOS-O3 film through second TEOS-O3 CVD where the ozone concentration is relatively high.
    Type: Application
    Filed: February 9, 2001
    Publication date: October 11, 2001
    Inventors: Toshie Kutsunai, Shinichiro Hayashi, Yuji Judai, Yoshihisa Nagano
  • Patent number: 6281534
    Abstract: A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75° C., and after 109 negative polarization switching pulses at 125° C.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: August 28, 2001
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Koji Arita, Shinichiro Hayashi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Publication number: 20010015451
    Abstract: A semiconductor memory device according to the present invention includes a memory cell capacitor for storing data thereon. The capacitor is made up of a first electrode connected to a contact plug, a second electrode and a capacitive insulating film interposed between the first and second electrodes. The first electrode includes a first barrier film in contact with the contact plug and a second barrier film, which is formed on the first barrier film and prevents the diffusion of oxygen. The second barrier film covers the upper and side faces of the first barrier film.
    Type: Application
    Filed: February 20, 2001
    Publication date: August 23, 2001
    Inventors: Yoshihisa Nagano, Tooru Nasu, Shinichiro Hayashi, Eiji Fujii
  • Publication number: 20010012698
    Abstract: A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1−x)(TayNb1−y)2O6, where 0≦x≦1.0 and 0≦y≦1.0; (BaxSr1−x)2(TayNb1−y)2O7, where 0≦x≦1.0 and 0≦y≦1.0; and (BaxSr1−x)2Bi2(TayNby−1)2O10, where 0≦x≦1.0 and 0≦y≦1.0. Thin films according to the invention have a relative dielectric constant ≧40, and preferably about 100.
    Type: Application
    Filed: March 2, 2001
    Publication date: August 9, 2001
    Applicant: Symetrix Corporation
    Inventors: Shinichiro Hayashi, Vikram Joshi, Narayan Solayappan, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Publication number: 20010011738
    Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.
    Type: Application
    Filed: January 14, 1999
    Publication date: August 9, 2001
    Inventors: SHINICHIRO HAYASHI, TATSUO OTSUKI, CARLOS A. PAZ DE ARAUJO
  • Patent number: 6265738
    Abstract: A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by carefully controlled drying, soft baking, and annealing conditions.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: July 24, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Shinichiro Hayashi, Tatsuo Otsuki
  • Patent number: 6255121
    Abstract: A method for forming an interface insulator layer in a ferroelectric FET memory, in which a liquid precursor is applied to a semiconductor substrate. Preferably, the liquid precursor is an enhanced metalorganic decomposition (“EMOD”) precursor, applied using a liquid-source misted deposition technique. Preferably, the EMOD precursor solution applied to the substrate contains metal ethylhexanoates containing metal moieties in relative molar proportions for forming an interface insulator layer containing ZrO2, CeO2, Y2O3 or (Ce1-xZrx)O2, wherein 0≦x≦1.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: July 3, 2001
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Koji Arita, Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
  • Patent number: 6198225
    Abstract: A thin film of ferroelectric layered superlattice material in a flat panel display device is energized to selectively influence the display image. In one embodiment, a voltage pulse causes the layered superlattice material to emit electrons that impinge upon a phosphor, causing the phosphor to emit light. In another embodiment, an electric potential creates a remanent polarization in the layered superlattice material, which exerts an electric field in liquid crystal layer, thereby influencing the transmissivity of light through the liquid crystal. The layered superlattice material is a metal oxide formed using an inventive liquid precursor containing an alkoxycarboxylate. The thin film thickness is preferably in the range 50-140 nm, so that polarizabilty and transparency of the thin film is enhanced. A display element may comprise a varistor device to prevent cross-talk between pixels and to enable sudden polarization switching. A functional gradient in the ferroelectric thin film enhances electron emission.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: March 6, 2001
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Gota Kano, Yasuhiro Shimada, Shinichiro Hayashi, Koji Arita, Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Larry D. McMillan
  • Patent number: 6151241
    Abstract: A ferroelectric field effect transistor memory cell includes a thin film varistor located between the gate electrode and the ferroelectric layer. The varistor protects the ferroelectric layer from disturb voltage pulses arising from memory read, write and sense operations. A second electrode is located between the thin film varistor and the ferroelectric layer. The thin film ferroelectric is positioned over the channel of a transistor to operate as a ferroelectric gate. For voltages at which disturb voltages are likely to occur, the thin film varistor has a resistance obeying a formula R.sub.d >10.times.1/(2.pi.fC.sub.F), where R.sub.d is resistivity of the thin film varistor, f is an operating frequency of said memory, and C.sub.F is the capacitance of the ferroelectric layer. For voltages at or near the read and write voltage of the memory, the thin film varistor has a resistance obeying a formula R.sub.d <0.1.times.1/(2.pi.fC.sub.F).
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: November 21, 2000
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
  • Patent number: 6143063
    Abstract: A substrate is located within a deposition chamber, the substrate defining a substrate plane. A liquid precursor is misted by ultrasonic or venturi apparatus, to produce a colloidal mist. The mist is generated, allowed to settle in a buffer chamber, filtered through a system up to 0.01 micron, and flowed into the deposition chamber between the substrate and barrier plate to deposit a liquid layer on the substrate. The liquid is dried to form a thin film of solid material on the substrate, which is then incorporated into an electrical component of an integrated circuit.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: November 7, 2000
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Shinichiro Hayashi, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 6133092
    Abstract: A liquid precursor containing thallium is applied to a first electrode, RTP baked at a temperature lower than 725.degree. C., and annealed at the same temperature for a time period from one to five hours to yield a ferroelectric layered superlattice material. A second electrode is formed to form a capacitor, and a second anneal is performed at a temperature lower than 725.degree. C. If the material is strontium bismuth thallium tantalate, the precursor contains (m-1) mole-equivalents of strontium for each of (2.2-x) mole-equivalents of bismuth, x mole-equivalents of thallium, and m mole-equivalents of tantalum, where m=2 and 0.0<x.ltoreq.2.2.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: October 17, 2000
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Shinichiro Hayashi, Carlos A. Paz de Araujo
  • Patent number: 6110889
    Abstract: Disclosed are peptide-based compositions and methods for inhibiting and modulating the actions of CXC intercrine molecules. The antileukinate peptides described inhibit IL-8, GRO and MIP2.beta. binding to neutrophils and neutrophil activation. The peptides are particularly advantageous as they inhibit IL-8-induced enzyme release at a 25 fold lower concentration than is required to inhibit chemotaxis, which makes them ideal for treating various inflammatory diseases and disorders including, amongst others, Adult Respiratory Distress Syndrome (ARDS), cystic fibrosis and chronic bronchitis. The invention further includes methods for inhibiting tumor cell growth by employing selected members of the disclosed group of peptides to inhibit .alpha.-chemokine binding to the tumor cell.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: August 29, 2000
    Assignee: Board of Regents, The University of Texas System
    Inventors: Edmund J. Miller, Shinichiro Hayashi