Patents by Inventor Shinji Baba
Shinji Baba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11049806Abstract: A semiconductor device includes a wiring substrate provided with a plurality of pads electrically connected to a semiconductor chip in a flip-chip interconnection. The wiring substrate includes a pad forming layer in which a signal pad configured to receive transmission of a first signal and a second pad configured to receive transmission of a second signal different from the first signal are formed and a first wiring layer located at a position closest to the pad forming layer. In the wiring layer, a via land overlapping with the signal pad, a wiring connected to the via land, and a wiring connected to the second pad and extending in an X direction are formed. In a Y direction intersecting the X direction, a width of the via land is larger than a width of the wiring. A wiring is adjacent to the via land and overlaps with the signal pad.Type: GrantFiled: March 29, 2019Date of Patent: June 29, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuyuki Nakagawa, Shinji Baba, Hiroshi Koizumi
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Patent number: 10714415Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.Type: GrantFiled: March 20, 2019Date of Patent: July 14, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
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Patent number: 10570795Abstract: An exhaust gas purifying facility of a combustion engine includes: a marine combustion engine; a reducing device for feeding urea water into an exhaust gas in an exhaust gas line of the marine combustion engine; and a generation device for generating the urea water from urea powder. The generation device includes a storage-generation tank device and an adjustment tank device capable of adjusting the density of the urea water. The storage-generation tank device has a storage-generation tank for storing the urea powder and feeding water to the urea powder for dissolution. The adjustment tank device has an adjustment tank for storing the urea water withdrawn from the storage-generation tank.Type: GrantFiled: December 5, 2016Date of Patent: February 25, 2020Assignee: HITACHI ZOSEN CORPORATIONInventors: Hiroaki Kawaguchi, Hiroshi Tanaka, Shinji Baba
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Publication number: 20190318990Abstract: A semiconductor device includes a wiring substrate provided with a plurality of pads electrically connected to a semiconductor chip in a flip-chip interconnection. The wiring substrate includes a pad forming layer in which a signal pad configured to receive transmission of a first signal and a second pad configured to receive transmission of a second signal different from the first signal are formed and a first wiring layer located at a position closest to the pad forming layer. In the wiring layer, a via land overlapping with the signal pad, a wiring connected to the via land, and a wiring connected to the second pad and extending in an X direction are formed. In a Y direction intersecting the X direction, a width of the via land is larger than a width of the wiring. A wiring is adjacent to the via land and overlaps with the signal pad.Type: ApplicationFiled: March 29, 2019Publication date: October 17, 2019Inventors: Kazuyuki NAKAGAWA, Shinji BABA, Hiroshi KOIZUMI
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Patent number: 10396044Abstract: A semiconductor device includes a wiring substrate including a first surface and a second surface opposite to the first surface, a semiconductor chip including a plurality of chip electrodes and mounted over the wiring substrate, a first capacitor arranged at a position overlapping with the semiconductor chip in plan view and incorporated in the wiring substrate, and a second capacitor arranged between the first capacitor and a peripheral portion of the wiring substrate in plan view. Also, the second capacitor is inserted in series connection into a signal transmission path through which an electric signal is input to or output from the semiconductor chip.Type: GrantFiled: October 15, 2015Date of Patent: August 27, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuyuki Nakagawa, Keita Tsuchiya, Yoshiaki Sato, Shinji Baba
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Publication number: 20190221509Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.Type: ApplicationFiled: March 20, 2019Publication date: July 18, 2019Applicants: RENESAS ELECTRONICS CORPORATION, RENESAS ELECTRONICS CORPORATIONInventors: Eiji HAYASHI, Kyo GO, Kozo HARADA, Shinji BABA
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Patent number: 10325841Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member.Type: GrantFiled: February 10, 2016Date of Patent: June 18, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuyuki Nakagawa, Katsushi Terajima, Keita Tsuchiya, Yoshiaki Sato, Hiroyuki Uchida, Yuji Kayashima, Shuuichi Kariyazaki, Shinji Baba
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Patent number: 10304768Abstract: A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer.Type: GrantFiled: May 25, 2018Date of Patent: May 28, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuyuki Nakagawa, Shinji Baba, Takeumi Kato
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Patent number: 10283444Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.Type: GrantFiled: October 27, 2017Date of Patent: May 7, 2019Assignee: Renesas Electronics CorporationInventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
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Publication number: 20180374788Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member.Type: ApplicationFiled: February 10, 2016Publication date: December 27, 2018Inventors: Kazuyuki NAKAGAWA, Katsushi TERAJIMA, Keita TSUCHIYA, Yoshiaki SATO, Hiroyuki UCHIDA, Yuji KAYASHIMA, Shuuichi KARIYAZAKI, Shinji BABA
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Publication number: 20180371975Abstract: An exhaust gas purifying facility of a combustion engine includes: a marine combustion engine; a reducing device for feeding urea water into an exhaust gas in an exhaust gas line of the marine combustion engine; and a generation device for generating the urea water from urea powder. The generation device includes a storage-generation tank device and an adjustment tank device capable of adjusting the density of the urea water. The storage-generation tank device has a storage-generation tank for storing the urea powder and feeding water to the urea powder for dissolution. The adjustment tank device has an adjustment tank for storing the urea water withdrawn from the storage-generation tank.Type: ApplicationFiled: December 5, 2016Publication date: December 27, 2018Inventors: Hiroaki KAWAGUCHI, Hiroshi TANAKA, Shinji BABA
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Patent number: 10134663Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.Type: GrantFiled: September 25, 2017Date of Patent: November 20, 2018Assignee: Renesas Electronics CorporationInventors: Shinji Baba, Toshihiro Iwasaki, Masaki Watanabe
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Publication number: 20180277473Abstract: A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer.Type: ApplicationFiled: May 25, 2018Publication date: September 27, 2018Inventors: Kazuyuki NAKAGAWA, Shinji BABA, Takeumi KATO
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Publication number: 20180254252Abstract: A semiconductor device includes a wiring substrate including a first surface and a second surface opposite to the first surface, a semiconductor chip including a plurality of chip electrodes and mounted over the wiring substrate, a first capacitor arranged at a position overlapping with the semiconductor chip in plan view and incorporated in the wiring substrate, and a second capacitor arranged between the first capacitor and a peripheral portion of the wiring substrate in plan view. Also, the second capacitor is inserted in series connection into a signal transmission path through which an electric signal is input to or output from the semiconductor chip.Type: ApplicationFiled: October 15, 2015Publication date: September 6, 2018Inventors: Kazuyuki NAKAGAWA, Keita TSUCHIYA, Yoshiaki SATO, Shinji BABA
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Patent number: 10056323Abstract: A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer.Type: GrantFiled: April 24, 2014Date of Patent: August 21, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuyuki Nakagawa, Shinji Baba, Takeumi Kato
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Patent number: 10037966Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.Type: GrantFiled: December 9, 2016Date of Patent: July 31, 2018Assignee: Renesas Electronics CorporationInventors: Toshihiro Iwasaki, Takeumi Kato, Takanori Okita, Yoshikazu Shimote, Shinji Baba, Kazuyuki Nakagawa, Michitaka Kimura
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Publication number: 20180068936Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.Type: ApplicationFiled: October 27, 2017Publication date: March 8, 2018Inventors: Eiji HAYASHI, Kyo GO, Kozo HARADA, Shinji BABA
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Publication number: 20180047695Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.Type: ApplicationFiled: October 30, 2017Publication date: February 15, 2018Applicant: Renesas Electronics CorporationInventors: Yoshikazu SHIMOTE, Shinji BABA, Toshihiro IWASAKI, Kazuyuki NAKAGAWA
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Publication number: 20180012831Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.Type: ApplicationFiled: September 25, 2017Publication date: January 11, 2018Inventors: Shinji BABA, Toshihiro IWASAKI, Masaki Watanabe
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Patent number: 9837369Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.Type: GrantFiled: September 27, 2013Date of Patent: December 5, 2017Assignee: Renesas Electronics CorporationInventors: Yoshikazu Shimote, Shinji Baba, Toshihiro Iwasaki, Kazuyuki Nakagawa