Patents by Inventor Shinji Baba

Shinji Baba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11049806
    Abstract: A semiconductor device includes a wiring substrate provided with a plurality of pads electrically connected to a semiconductor chip in a flip-chip interconnection. The wiring substrate includes a pad forming layer in which a signal pad configured to receive transmission of a first signal and a second pad configured to receive transmission of a second signal different from the first signal are formed and a first wiring layer located at a position closest to the pad forming layer. In the wiring layer, a via land overlapping with the signal pad, a wiring connected to the via land, and a wiring connected to the second pad and extending in an X direction are formed. In a Y direction intersecting the X direction, a width of the via land is larger than a width of the wiring. A wiring is adjacent to the via land and overlaps with the signal pad.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 29, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Shinji Baba, Hiroshi Koizumi
  • Patent number: 10714415
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: July 14, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
  • Patent number: 10570795
    Abstract: An exhaust gas purifying facility of a combustion engine includes: a marine combustion engine; a reducing device for feeding urea water into an exhaust gas in an exhaust gas line of the marine combustion engine; and a generation device for generating the urea water from urea powder. The generation device includes a storage-generation tank device and an adjustment tank device capable of adjusting the density of the urea water. The storage-generation tank device has a storage-generation tank for storing the urea powder and feeding water to the urea powder for dissolution. The adjustment tank device has an adjustment tank for storing the urea water withdrawn from the storage-generation tank.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: February 25, 2020
    Assignee: HITACHI ZOSEN CORPORATION
    Inventors: Hiroaki Kawaguchi, Hiroshi Tanaka, Shinji Baba
  • Publication number: 20190318990
    Abstract: A semiconductor device includes a wiring substrate provided with a plurality of pads electrically connected to a semiconductor chip in a flip-chip interconnection. The wiring substrate includes a pad forming layer in which a signal pad configured to receive transmission of a first signal and a second pad configured to receive transmission of a second signal different from the first signal are formed and a first wiring layer located at a position closest to the pad forming layer. In the wiring layer, a via land overlapping with the signal pad, a wiring connected to the via land, and a wiring connected to the second pad and extending in an X direction are formed. In a Y direction intersecting the X direction, a width of the via land is larger than a width of the wiring. A wiring is adjacent to the via land and overlaps with the signal pad.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 17, 2019
    Inventors: Kazuyuki NAKAGAWA, Shinji BABA, Hiroshi KOIZUMI
  • Patent number: 10396044
    Abstract: A semiconductor device includes a wiring substrate including a first surface and a second surface opposite to the first surface, a semiconductor chip including a plurality of chip electrodes and mounted over the wiring substrate, a first capacitor arranged at a position overlapping with the semiconductor chip in plan view and incorporated in the wiring substrate, and a second capacitor arranged between the first capacitor and a peripheral portion of the wiring substrate in plan view. Also, the second capacitor is inserted in series connection into a signal transmission path through which an electric signal is input to or output from the semiconductor chip.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Keita Tsuchiya, Yoshiaki Sato, Shinji Baba
  • Publication number: 20190221509
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Application
    Filed: March 20, 2019
    Publication date: July 18, 2019
    Applicants: RENESAS ELECTRONICS CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji HAYASHI, Kyo GO, Kozo HARADA, Shinji BABA
  • Patent number: 10325841
    Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Katsushi Terajima, Keita Tsuchiya, Yoshiaki Sato, Hiroyuki Uchida, Yuji Kayashima, Shuuichi Kariyazaki, Shinji Baba
  • Patent number: 10304768
    Abstract: A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: May 28, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Shinji Baba, Takeumi Kato
  • Patent number: 10283444
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 7, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
  • Publication number: 20180374788
    Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member.
    Type: Application
    Filed: February 10, 2016
    Publication date: December 27, 2018
    Inventors: Kazuyuki NAKAGAWA, Katsushi TERAJIMA, Keita TSUCHIYA, Yoshiaki SATO, Hiroyuki UCHIDA, Yuji KAYASHIMA, Shuuichi KARIYAZAKI, Shinji BABA
  • Publication number: 20180371975
    Abstract: An exhaust gas purifying facility of a combustion engine includes: a marine combustion engine; a reducing device for feeding urea water into an exhaust gas in an exhaust gas line of the marine combustion engine; and a generation device for generating the urea water from urea powder. The generation device includes a storage-generation tank device and an adjustment tank device capable of adjusting the density of the urea water. The storage-generation tank device has a storage-generation tank for storing the urea powder and feeding water to the urea powder for dissolution. The adjustment tank device has an adjustment tank for storing the urea water withdrawn from the storage-generation tank.
    Type: Application
    Filed: December 5, 2016
    Publication date: December 27, 2018
    Inventors: Hiroaki KAWAGUCHI, Hiroshi TANAKA, Shinji BABA
  • Patent number: 10134663
    Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Baba, Toshihiro Iwasaki, Masaki Watanabe
  • Publication number: 20180277473
    Abstract: A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer.
    Type: Application
    Filed: May 25, 2018
    Publication date: September 27, 2018
    Inventors: Kazuyuki NAKAGAWA, Shinji BABA, Takeumi KATO
  • Publication number: 20180254252
    Abstract: A semiconductor device includes a wiring substrate including a first surface and a second surface opposite to the first surface, a semiconductor chip including a plurality of chip electrodes and mounted over the wiring substrate, a first capacitor arranged at a position overlapping with the semiconductor chip in plan view and incorporated in the wiring substrate, and a second capacitor arranged between the first capacitor and a peripheral portion of the wiring substrate in plan view. Also, the second capacitor is inserted in series connection into a signal transmission path through which an electric signal is input to or output from the semiconductor chip.
    Type: Application
    Filed: October 15, 2015
    Publication date: September 6, 2018
    Inventors: Kazuyuki NAKAGAWA, Keita TSUCHIYA, Yoshiaki SATO, Shinji BABA
  • Patent number: 10056323
    Abstract: A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: August 21, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Shinji Baba, Takeumi Kato
  • Patent number: 10037966
    Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 31, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iwasaki, Takeumi Kato, Takanori Okita, Yoshikazu Shimote, Shinji Baba, Kazuyuki Nakagawa, Michitaka Kimura
  • Publication number: 20180068936
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Application
    Filed: October 27, 2017
    Publication date: March 8, 2018
    Inventors: Eiji HAYASHI, Kyo GO, Kozo HARADA, Shinji BABA
  • Publication number: 20180047695
    Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.
    Type: Application
    Filed: October 30, 2017
    Publication date: February 15, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshikazu SHIMOTE, Shinji BABA, Toshihiro IWASAKI, Kazuyuki NAKAGAWA
  • Publication number: 20180012831
    Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 11, 2018
    Inventors: Shinji BABA, Toshihiro IWASAKI, Masaki Watanabe
  • Patent number: 9837369
    Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshikazu Shimote, Shinji Baba, Toshihiro Iwasaki, Kazuyuki Nakagawa