Patents by Inventor Shinji Maekawa

Shinji Maekawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160211278
    Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.
    Type: Application
    Filed: March 18, 2016
    Publication date: July 21, 2016
    Inventors: Hiroshi SHIBATA, Shinji MAEKAWA
  • Patent number: 9362410
    Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 7, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroshi Shibata, Shinji Maekawa
  • Publication number: 20160099356
    Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.
    Type: Application
    Filed: December 18, 2015
    Publication date: April 7, 2016
    Inventors: Hiroshi SHIBATA, Shinji MAEKAWA
  • Patent number: 9237657
    Abstract: The present invention provides a thin wiring pattern such as wiring formed by discharging a droplet. In the present invention, a porous (including microporous) substance is formed as a base film in forming pattern by using a droplet discharge method (also referred to as an ink-jetting method). One feature of a wiring substrate according to the present invention provides a porous film and a conductive layer thereon. One feature of a semiconductor device of the present invention provides a thin film transistor in which a gate electrode is formed by the conductive layer having the above-described structure.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: January 12, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO. LTD.
    Inventors: Shinji Maekawa, Yasuyuki Arai
  • Patent number: 9219157
    Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: December 22, 2015
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Hiroshi Shibata, Shinji Maekawa
  • Patent number: 9202728
    Abstract: A substrate mounting mechanism on which a target substrate is placed is provided. The substrate mounting mechanism includes a heater plate, which has a substrate mounting surface on which the target substrate is placed and has a heater embedded therein to heat the substrate to a deposition temperature at which a film is deposited. The substrate mounting mechanism also includes a temperature control jacket, which is formed to cover at least a surface of the heater plate other than the substrate mounting surface and adjusts the temperature to a non-deposition temperature below the deposition temperature.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: December 1, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masamichi Hara, Atsushi Gomi, Shinji Maekawa, Satoshi Taga, Kaoru Yamamoto
  • Patent number: 9176073
    Abstract: The present invention provides an evaluation substrate for evaluating a foreign object defect included in an organic material, a defect examination method and defect detection device. The evaluation substrate of the present invention includes a substrate, a first film arranged on the substrate, and a second film arranged on the first film, wherein a film containing an organic material is formed on the second film; the first film being set lower than an etching rate of the second film with respect to an etchant used in etching the second film, the first film having the same or a smaller detection lower limit value of an optically detectable defect than a detection lower limit value of a defect of the second film; and a thickness of the second film being set to a value near an optically measured lowest or minimum Haze value.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: November 3, 2015
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Shinji Maekawa, Masafumi Sato
  • Patent number: 9123625
    Abstract: The invention provides an active matrix EL display device which can perform a clear multi-gray scale color display. In particular, the invention provides a large active matrix EL display device at low cost by a manufacturing method which can selectively form a pattern. Power supply lines in a pixel portion are arranged in matrix by the manufacturing method which can selectively form a pattern. Further, capacitance between wirings is reduced by providing a longer distance between adjacent wirings by the manufacturing method which can selectively form a pattern.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: September 1, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasunori Yoshida, Hajime Kimura, Shinji Maekawa, Osamu Nakamura, Shunpei Yamazaki
  • Patent number: 8997570
    Abstract: An acceleration sensor having a high impact resistance to prevent breakage under excessive acceleration, but can stably exert a sensing performance. The acceleration sensor is formed of an SOI substrate of a three-layered structure including a silicon layer (active layer silicon), a silicon oxide layer, and a silicon layer (substrate silicon). The acceleration sensor includes frame parts, a plurality of beam parts, the beam parts projecting inward from the frame part, and a weight part supported by the beam parts. A strain sensing part is provided on each of the beam parts. A width W of each of the beam parts, a length I of each of the beam parts, and an inner frame length L of the frame part satisfy the following relationships of Expressions (1) and (2). 2<L/I?2.82??Expression (1) I/W?3.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: April 7, 2015
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventor: Shinji Maekawa
  • Patent number: 8987068
    Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Keitaro Imai
  • Patent number: 8912546
    Abstract: The present invention provides a technique by which a component forming a display device, such as a wiring can be formed with good adhesion. In the invention, a component forming a thin film transistor, a display device, or the like is formed with a material which is the same as at least one of the substances forming the formation subject surface added (mixed); thus, adhesion between the component and the formation subject is improved. An insulating layer formed over the component is formed with a laminate of a first insulating layer containing an organic material and a second insulating layer containing an inorganic material; thus, the insulating layer sufficiently covers irregularities on the surface of the component, and is also dense enough so as to be reliable as an insulating layer.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shinji Maekawa
  • Publication number: 20140319491
    Abstract: The invention provides an active matrix EL display device which can perform a clear multi-gray scale color display. In particular, the invention provides a large active matrix EL display device at low cost by a manufacturing method which can selectively form a pattern. Power supply lines in a pixel portion are arranged in matrix by the manufacturing method which can selectively form a pattern. Further, capacitance between wirings is reduced by providing a longer distance between adjacent wirings by the manufacturing method which can selectively form a pattern.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 30, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yasunori Yoshida, Hajime Kimura, Shinji Maekawa, Osamu Nakamura, Shunpei Yamazaki
  • Patent number: 8742421
    Abstract: An object of the present invention is to provide a display device which can be manufactured with usability of a material improved and with a manufacturing step simplified and to provide a manufacturing technique thereof. One feature of a display device of the present invention is to comprise an insulating layer having an opening, a first conductive layer formed in the opening, and a second conductive layer formed over the insulating layer and the first conductive layer, wherein the first conductive layer is wider and thicker than the second conductive layer, and the second conductive layer is formed by spraying a droplet including a conductive material.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideaki Kuwabara, Shinji Maekawa, Gen Fujii, Toshiyuki Isa
  • Patent number: 8717269
    Abstract: The invention provides an active matrix EL display device which can perform a clear multi-gray scale color display. In particular, the invention provides a large active matrix EL display device at low cost by a manufacturing method which can selectively form a pattern. Power supply lines in a pixel portion are arranged in matrix by the manufacturing method which can selectively form a pattern. Further, capacitance between wirings is reduced by providing a longer distance between adjacent wirings by the manufacturing method which can selectively form a pattern.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: May 6, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasunori Yoshida, Hajime Kimura, Shinji Maekawa, Osamu Nakamura, Shunpei Yamazaki
  • Publication number: 20140080238
    Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 20, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Shinji MAEKAWA, Makoto FURUNO, Osamu NAKAMURA, Keitaro IMAI
  • Publication number: 20140048861
    Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.
    Type: Application
    Filed: November 1, 2013
    Publication date: February 20, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hiroshi SHIBATA, Shinji MAEKAWA
  • Patent number: 8637397
    Abstract: To provide a method of manufacturing a through hole electrode substrate which comprises forming a plurality of through holes passing through the front and back of a wafer-shaped substrate, forming an insulation film on a surface of the substrate and the though hole, forming a seed layer from a metal on at least one side of the substrate and/or the through hole, forming a metal layer having a cap shape on a bottom part of the through hole on a surface on which the seed layer is formed by an electrolytic plating method supplying direct current to the seed layer for a first time period, and filling a metal material into the plurality of through holes by an electrolytic plating method supplying a pulse current to the seed layer and the metal layer.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: January 28, 2014
    Assignee: Dai Nippon Printing Co., Ltd
    Inventors: Shinji Maekawa, Myuki Suzuki
  • Patent number: 8629442
    Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Keitaro Imai
  • Patent number: 8624252
    Abstract: The invention provides a manufacturing method of a substrate having a film pattern including an insulating film, a semiconductor film, a conductive film and the like by simple steps, and also a manufacturing method of a semiconductor device which is low in cost with high throughput and yield. According to the invention, after forming a first protective film which has low wettability on a substrate, a material which has high wettability is applied or discharged on an outer edge of a first mask pattern, thereby a film pattern and a substrate having the film pattern are formed.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Gen Fujii, Hiroko Shiroguchi, Masafumi Morisue
  • Patent number: 8619219
    Abstract: As a wiring becomes thicker, discontinuity of an insulating film covering the wiring has become a problem. It is difficult to form a wiring with width thin enough for a thin film transistor used for a current high definition display device. As a wiring is made thinner, signal delay due to wiring resistance has become a problem. In view of the above problems, the invention provides a structure in which a conductive film is formed in a hole of an insulating film, and the surfaces of the conductive film and the insulating film are flat. As a result, discontinuity of thin films covering a conductive film and an insulating film can be prevented. A wiring can be made thinner by controlling the width of the hole. Further, a wiring can be made thicker by controlling the depth of the hole.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: December 31, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Yohei Kanno