Patents by Inventor Shinji Maekawa
Shinji Maekawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130341627Abstract: The invention provides an active matrix EL display device which can perform a clear multi-gray scale color display. In particular, the invention provides a large active matrix EL display device at low cost by a manufacturing method which can selectively form a pattern. Power supply lines in a pixel portion are arranged in matrix by the manufacturing method which can selectively form a pattern. Further, capacitance between wirings is reduced by providing a longer distance between adjacent wirings by the manufacturing method which can selectively form a pattern.Type: ApplicationFiled: August 20, 2013Publication date: December 26, 2013Applicant: Semiconductor Energy Laboratory Co., LtdInventors: Yasunori YOSHIDA, Hajime KIMURA, Shinji MAEKAWA, Osamu NAKAMURA, Shunpei YAMAZAKI
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Patent number: 8575618Abstract: The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the region exposed to laser light to be left and realizing a source wiring and a drain wiring having a more microscopic pattern than the pattern itself formed by discharging. One feature of the source wiring and the drain wiring is that the source wiring and the drain wiring cross an island-like semiconductor layer and overlap it.Type: GrantFiled: June 25, 2012Date of Patent: November 5, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinji Maekawa, Hideaki Kuwabara
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Patent number: 8575696Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.Type: GrantFiled: April 27, 2007Date of Patent: November 5, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroshi Shibata, Shinji Maekawa
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Patent number: 8570630Abstract: A piezoelectric mirror device (11) comprises a frame portion (12) having a centrally located opening (13), a mirror portion (14) positioned at the opening (13), a pair of mirror support portions (15) adapted to support the mirror portion (14) rotatably relative the frame portion (12) and a pair of drive portions (16) that is a multilayer structure of lower electrodes (17), piezoelectric element (18) and an upper electrode (19). The mirror support portions (15) are formed of a material having a Young's modulus of up to 160 GPa, and the frame portion (12) includes a cutout (13a) at a part of a site wherein there are the drive portions (16) positioned. The cutout (13a) is in contact with the opening (13).Type: GrantFiled: April 12, 2012Date of Patent: October 29, 2013Assignee: Dai Nippon Printing Co., Ltd.Inventor: Shinji Maekawa
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Patent number: 8563438Abstract: A manufacturing method of a semiconductor device of which cost can be suppressed by using a nanoimprinting method is provided. In the invention, a gate insulating film, a conductive film, and a resist are formed in sequence over a semiconductor film and a resist is hardened while pressing a mold formed with a pattern to the resist. Therefore, the pattern is transferred to the resist, the surface of the resist to which the pattern is transferred is ashed until a part of the conductive film is exposed, the resist having the ashed surface is used a mask, and the conductive film is etched.Type: GrantFiled: December 29, 2009Date of Patent: October 22, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shinji Maekawa
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Publication number: 20130258330Abstract: The present invention provides an evaluation substrate for evaluating a foreign object defect included in an organic material, a defect examination method and defect detection device. The evaluation substrate of the present invention includes a substrate, a first film arranged on the substrate, and a second film arranged on the first film, wherein a film containing an organic material is formed on the second film; the first film being set lower than an etching rate of the second film with respect to an etchant used in etching the second film, the first film having the same or a smaller detection lower limit value of an optically detectable defect than a detection lower limit value of a defect of the second film; and a thickness of the second film being set to a value near an optically measured lowest or minimum Haze value.Type: ApplicationFiled: May 28, 2013Publication date: October 3, 2013Applicant: DAI NIPPON PRINTING CO., LTD.Inventors: Shinji MAEKAWA, Masafumi SATO
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Patent number: 8547315Abstract: The invention provides an active matrix EL display device which can perform a clear multi-gray scale color display. In particular, the invention provides a large active matrix EL display device at low cost by a manufacturing method which can selectively form a pattern. Power supply lines in a pixel portion are arranged in matrix by the manufacturing method which can selectively form a pattern. Further, capacitance between wirings is reduced by providing a longer distance between adjacent wirings by the manufacturing method which can selectively form a pattern.Type: GrantFiled: July 3, 2012Date of Patent: October 1, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasunori Yoshida, Hajime Kimura, Shinji Maekawa, Osamu Nakamura, Shunpei Yamazaki
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Patent number: 8539655Abstract: A piezoelectric mirror device fabrication process, including: dividing a silicon wafer into a multiplicity of segments, wherein on one surface of said silicon wafer per segment, a pair of lower electrodes, a mirror portion positioned between said lower electrodes and a pair of mirror support portions adapted to join said mirror portion to said lower electrodes are formed of an electrically conductive material having a Young's modulus of up to 160 GPa and a melting point higher than that of a piezoelectric element to be formed later; stacking the piezoelectric element and an upper electrode on said lower electrodes; removing the silicon wafer in a desired pattern from another surface of said silicon wafer per segment, and obtaining a multiplicity of piezoelectric mirror devices by dicing said multiplicity of piezoelectric mirror devices into individual ones.Type: GrantFiled: April 1, 2011Date of Patent: September 24, 2013Assignee: Dai Nippon Printing Co., Ltd.Inventor: Shinji Maekawa
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Patent number: 8535965Abstract: The present invention provides a method for forming by plasma CVD a silicon nitride film that can be formed over heat-sensitive elements as well as an electroluminescent element and that has favorable barrier characteristics. Further, the present invention also provides a semiconductor device, a display device and a light-emitting display device formed by using the silicon nitride film. In the method for forming a silicon nitride film by plasma CVD, silane (SiH4), nitrogen (N2) and a rare gas are introduced into a deposition chamber in depositing, and the reaction pressure is within the range from 0.01 Torr to 0.1 Torr.Type: GrantFiled: July 2, 2012Date of Patent: September 17, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinji Maekawa, Tetsuya Kakehata, Yuuichi Takehara
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Patent number: 8518760Abstract: The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer.Type: GrantFiled: March 17, 2011Date of Patent: August 27, 2013Assignee: Semiconductor Energy Co., Ltd.Inventors: Shunpei Yamazaki, Osamu Nakamura, Shinji Maekawa, Gen Fujii, Toshiyuki Isa
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Patent number: 8461013Abstract: An IC card is more expensive than a magnetic card, and an electronic tag is also more expensive as a substitute for bar codes. Therefore, the present invention provides an extremely thin integrated circuit that can be mass-produced at low cost unlike a chip of a conventional silicon wafer, and a manufacturing method thereof. One feature of the present invention is that a thin integrated circuit is formed by a formation method that can form a pattern selectively, on a glass substrate, a quartz substrate, a stainless substrate, a substrate made of synthetic resin having flexibility, such as acryl, or the like except for a bulk substrate. Further, another feature of the present invention is that an ID chip in which a thin film integrated circuit and an antenna according to the present invention are mounted is formed.Type: GrantFiled: May 10, 2010Date of Patent: June 11, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinji Maekawa, Gen Fujii, Junya Maruyama, Toru Takayama, Yumiko Fukumoto, Yasuyuki Arai
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Patent number: 8455335Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed.Type: GrantFiled: November 9, 2010Date of Patent: June 4, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinji Maekawa, Hidekazu Miyairi
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Patent number: 8445901Abstract: In view of the problem that an organic semiconductor layer of an organic TFT is likely to deteriorate due to water, light, oxygen, or the like, it is an object of the present invention to simplify a manufacturing step and to provide a method for manufacturing a semiconductor device having an organic TFT with high reliability. According to the invention, a semiconductor layer containing an organic material is formed by patterning using a mask, and thus an organic TFT is completed in the state where the mask is not removed but to remain over the semiconductor layer. In addition, a semiconductor layer can be protected from deterioration due to water, light, oxygen, or the like by using the remaining mask.Type: GrantFiled: May 3, 2012Date of Patent: May 21, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shinji Maekawa
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Publication number: 20130001560Abstract: The invention provides a manufacturing method of a substrate having a film pattern including an insulating film, a semiconductor film, a conductive film and the like by simple steps, and also a manufacturing method of a semiconductor device which is low in cost with high throughput and yield. According to the invention, after forming a first protective film which has low wettability on a substrate, a material which has high wettability is applied or discharged on an outer edge of a first mask pattern, thereby a film pattern and a substrate having the film pattern are formed.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shinji MAEKAWA, Gen FUJII, Hiroko SHIROGUCHI, Masafumi MORISUE
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Publication number: 20120329276Abstract: To provide a method of manufacturing a through hole electrode substrate which comprises forming a plurality of through holes passing through the front and back of a wafer-shaped substrate, forming an insulation film on a surface of the substrate and the though hole, forming a seed layer from a metal on at least one side of the substrate and/or the through hole, forming a metal layer having a cap shape on a bottom part of the through hole on a surface on which the seed layer is formed by an electrolytic plating method supplying direct current to the seed layer for a first time period, and filling a metal material into the plurality of through holes by an electrolytic plating method supplying a pulse current to the seed layer and the metal layer.Type: ApplicationFiled: September 7, 2012Publication date: December 27, 2012Applicant: DAI NIPPON PRINTING CO., LTD.Inventors: Shinji MAEKAWA, Myuki SUZUKI
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Patent number: 8322847Abstract: When using a liquid droplet ejection method, a conventional photomask is not required, however, it is required instead that a moving path of a nozzle or a substrate is controlled with accuracy at least in ejecting liquid droplets. According to the characteristics of compositions to be ejected or their pattern, such ejection conditions are desirably set as the moving rate of a nozzle or a substrate, ejection quantity, ejection distance and ejection rate of compositions, atmosphere of the space that the compositions are ejected, the temperature and moisture of the space, and heating temperature of the substrate.Type: GrantFiled: March 16, 2011Date of Patent: December 4, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Yasuyuki Arai, Shinji Maekawa, Yohei Kanno
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Patent number: 8310474Abstract: When semi-amorphous TFTs are used for forming a signal line driver circuit and a pixel, a large amplitude is required for driving the pixel, and a large power supply voltage is thus needed. On the other hand, when a shift register is made up of transistors having a single conductivity, a bootstrap circuit is required, and a voltage over a power supply is applied to a specific element. Therefore, not both the driving amplitude and the reliability can be achieved with a single power supply. According to the invention, a level shifter having a single conductivity is provided to solve such a problem.Type: GrantFiled: February 17, 2009Date of Patent: November 13, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Jun Koyama, Keitaro Imai, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Shunpei Yamazaki
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Publication number: 20120282717Abstract: As a wiring becomes thicker, discontinuity of an insulating film covering the wiring has become a problem. It is difficult to form a wiring with width thin enough for a thin film transistor used for a current high definition display device. As a wiring is made thinner, signal delay due to wiring resistance has become a problem. In view of the above problems, the invention provides a structure in which a conductive film is formed in a hole of an insulating film, and the surfaces of the conductive film and the insulating film are flat. As a result, discontinuity of thin films covering a conductive film and an insulating film can be prevented. A wiring can be made thinner by controlling the width of the hole. Further, a wiring can be made thicker by controlling the depth of the hole.Type: ApplicationFiled: July 19, 2012Publication date: November 8, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Shinji Maekawa, Yohei Kanno
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Publication number: 20120276960Abstract: The invention provides an active matrix EL display device which can perform a clear multi-gray scale color display. In particular, the invention provides a large active matrix EL display device at low cost by a manufacturing method which can selectively form a pattern. Power supply lines in a pixel portion are arranged in matrix by the manufacturing method which can selectively form a pattern. Further, capacitance between wirings is reduced by providing a longer distance between adjacent wirings by the manufacturing method which can selectively form a pattern.Type: ApplicationFiled: July 3, 2012Publication date: November 1, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yasunori YOSHIDA, Hajima KIMURA, Shinji MAEKAWA, Osamu NAKAMURA, Shunpei YAMAZAKI
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Patent number: 8300290Abstract: A piezoelectric mirror device (11) comprises a frame portion (12) having a centrally located opening (13), a mirror portion (14) positioned at the opening (13), a pair of mirror support portions (15) adapted to support the mirror portion (14) rotatably relative the frame portion (12) and a pair of drive portions (16) that is a multilayer structure of lower electrodes (17), piezoelectric element (18) and an upper electrode (19). The mirror support portions (15) are formed of a material having a Young's modulus of up to 160 GPa, and the frame portion (12) includes a cutout (13a) at a part of a site wherein there are the drive portions (16) positioned. The cutout (13a) is in contact with the opening (13).Type: GrantFiled: June 4, 2008Date of Patent: October 30, 2012Assignee: Dai Nippon Printing Co., Ltd.Inventor: Shinji Maekawa