Patents by Inventor Shinsuke Harada
Shinsuke Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090134402Abstract: In the SiC vertical MOSFET having a low-concentration p-type deposition film provided therein with a channel region and a base region resulting from reverse-implantation to n-type through ion implantation, dielectric breakdown of gate oxide film used to occur at the time of off, thereby preventing a further blocking voltage enhancement. This problem has been resolved by interposing of a low-concentration n-type deposition film between a low-concentration p-type deposition film and a high-concentration gate layer and selectively forming of a base region resulting from reverse-implantation to n-type through ion implantation in the low-concentration p-type deposition film so that the thickness of deposition film between the high-concentration gate layer and each of channel region and gate oxide layer is increased.Type: ApplicationFiled: September 30, 2005Publication date: May 28, 2009Applicant: National Inst of Adv Industrial Science & TechInventors: Tsutomu Yatsuo, Shinsuke Harada, Mitsuo Okamoto, Kenji Fukuda
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Patent number: 7538352Abstract: In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the end semiconductor device can be improved by decreasing the roughness of the silicon carbide semiconductor substrate surface. The semiconductor device of this invention is a Schottky barrier diode or a p-n type diode comprising at least one of a p type semiconductor region and n type semiconductor region selectively formed in a silicon carbide semiconductor region having an outermost surface layer surface that is a (000-1) surface or a surface inclined at an angle to the (000-1) surface, and a metal electrode formed on the outermost surface layer surface, that controls a direction in which electric current flows in a direction perpendicular to the outermost surface layer surface from application of a voltage to the metal electrode.Type: GrantFiled: November 25, 2003Date of Patent: May 26, 2009Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Kenji Fukuda, Ryoji Kosugi, Junji Senzaki, Shinsuke Harada
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Publication number: 20090072244Abstract: The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.Type: ApplicationFiled: January 16, 2007Publication date: March 19, 2009Applicant: National Institute of Advanced Ind. Sci. & TechInventors: Shinsuke Harada, Makoto Katou, Kenji Fukuda, Tsutomu Yatsuo
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Publication number: 20090057686Abstract: In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the end semiconductor device can be improved by decreasing the roughness of the silicon carbide semiconductor substrate surface. The semiconductor device of this invention is a Schottky barrier diode or a p-n type diode comprising at least one of a p type semiconductor region and n type semiconductor region selectively formed in a silicon carbide semiconductor region having an outermost surface layer surface that is a (000-1) surface or a surface inclined at an angle to the (000-1) surface, and a metal electrode formed on the outermost surface layer surface, that controls a direction in which electric current flows in a direction perpendicular to the outermost surface layer surface from application of a voltage to the metal electrode.Type: ApplicationFiled: October 30, 2008Publication date: March 5, 2009Applicant: National Institute of Adv. Industrial Sci. & Tech.Inventors: Kenji FUKUDA, Ryoji Kosugi, Junji Senzaki, Shinsuke Harada
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Publication number: 20080203400Abstract: A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.Type: ApplicationFiled: February 4, 2008Publication date: August 28, 2008Applicant: National Institute of Advanced Indust. Sci & TechInventors: Kenji Fukuda, Junji Senzaki, Shinsuke Harada, Makoto Kato, Tsutomu Yatsuo, Mitsuo Okamoto
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Patent number: 7313138Abstract: A routing device includes a memory for storing routing entries in a routing table and a cache memory for storing some of routing entries present in the memory together with a mask length of a destination address as a cache entry. A high-speed retrieval section retrieves the cache entry corresponding to the destination address by referencing the cache memory based on the destination address of an input packet. An ordinary retrieval section retrieves the routing entry corresponding to the destination address by referencing the memory. A processing section writes the cache entry into the cache memory based on the routing entry retrieved by the ordinary retrieval section. The router device enables routing without using a routing entry that should not be used in the routing originally even when part of the routing table is cached.Type: GrantFiled: June 17, 2003Date of Patent: December 25, 2007Assignee: NEC CorporationInventors: Shinsuke Harada, Takeharu Yasuda
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Patent number: 7265388Abstract: A semiconductor device formed on a silicon carbide semiconductor substrate comprises an epitaxial layer formed on a surface sloping (or inclining) by 0 to less than 1 degree from a (000-1) face of the silicon carbide semiconductor substrate, wherein at least one of a P type semiconductor area or an N type semiconductor area is selectively formed in the epitaxial layer by ion implantation, a metal electrode is formed so as to contact a surface layer of the P type semiconductor area or the N type semiconductor area, a rectification function is shown between the metal electrode and the P type semiconductor area or the N type semiconductor area, and the semiconductor device is formed on the silicon carbide semiconductor substrate of a Schottky barrier diode or a PN type diode.Type: GrantFiled: August 30, 2004Date of Patent: September 4, 2007Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Kenji Fukuda, Ryouji Kosugi, Shinsuke Harada, Junji Senzaki, Kazutoshi Kojima, Satoshi Kuroda
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Patent number: 7256082Abstract: A method of manufacturing a semiconductor device that provides a semiconductor device having improved channel mobility includes a process of forming a gate insulation film of silicon oxide film, silicon nitride film or silicon oxide nitride film or the like on a silicon oxide substrate, and following formation of the gate insulation film on the silicon oxide substrate with heat treatment for a given time at a temperature range of 900° C. to 1000° C. in an atmosphere containing not less than 25% H2O (water).Type: GrantFiled: September 10, 2002Date of Patent: August 14, 2007Assignees: National Institute of Advanced Industrial Science and Technology, Sanyo Electric Co., Ltd.Inventors: Ryoji Kosugi, Kenji Fukuda, Junji Senzaki, Mitsuo Okamoto, Shinsuke Harada, Seiji Suzuki
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Publication number: 20060151806Abstract: In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the end semiconductor device can be improved by decreasing the roughness of the silicon carbide semiconductor substrate surface. The semiconductor device of this invention is a Schottky barrier diode or a p-n type diode comprising at least one of a p type semiconductor region and n type semiconductor region selectively formed in a silicon carbide semiconductor region having an outermost surface layer surface that is a (000-1) surface or a surface inclined at an angle to the (000-1) surface, and a metal electrode formed on the outermost surface layer surface, that controls a direction in which electric current flows in a direction perpendicular to the outermost surface layer surface from application of a voltage to the metal electrode.Type: ApplicationFiled: November 25, 2003Publication date: July 13, 2006Applicant: NATIONAL INSTITUTE OF ADV. INDUSTRIAL SCI. & TECHInventors: Kenji Fukuda, Ryoji Kosugi, Junji Senzaki, Shinsuke Harada
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Publication number: 20060057796Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.Type: ApplicationFiled: October 3, 2003Publication date: March 16, 2006Inventors: Shinsuke Harada, Tsutomu Yatsuo, Kenji Fukuda, Mitsuo Okamoto, Kazuhiro Adachi
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Publication number: 20050077591Abstract: A semiconductor device formed on a silicon carbide semiconductor substrate comprises an epitaxial layer formed on a surface sloping (or inclining) by 0 to less than 1 degree from a (000-1) face of the silicon carbide semiconductor substrate, wherein at least one of a P type semiconductor area or an N type semiconductor area is selectively formed in the epitaxial layer by ion implantation, a metal electrode is formed so as to contact a surface layer of the P type semiconductor area or the N type semiconductor area, a rectification function is shown between the metal electrode and the P type semiconductor area or the N type semiconductor area, and the semiconductor device is formed on the silicon carbide semiconductor substrate of a Schottky barrier diode or a PN type diode.Type: ApplicationFiled: August 30, 2004Publication date: April 14, 2005Inventors: Kenji Fukuda, Ryouji Kosugi, Shinsuke Harada, Junji Senzaki, Kazutoshi Kojima, Satoshi Kuroda
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Publication number: 20040242022Abstract: A method of manufacturing a semiconductor device that provides a semiconductor device having improved channel mobility includes a process of forming a gate insulation film of silicon oxide film, silicon nitride film or silicon oxide nitride film or the like on a silicon oxide substrate, and following formation of the gate insulation film on the silicon oxide substrate with heat treatment for a given time at a temperature range of 900° C. to 1000° C. in an atmosphere containing not less than 25% H2O (water).Type: ApplicationFiled: July 21, 2004Publication date: December 2, 2004Inventors: Ryoji Kosugi, Kenji Fukuda, Junji Senzaki, Mitsuo Okamoto, Shinsuke Harada, Seiji Suzuki
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Patent number: 6812102Abstract: In a semiconductor device using a silicon carbide substrate (1), the object of the present invention is to provide a method of manufacturing a semiconductor device that is a buried channel region type transistor having hot-carrier resistance, high punch-through resistance and high channel mobility. This is achieved by using a method of manufacturing a buried channel type transistor using a P-type silicon carbide substrate that includes a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer. The gate insulation layer is formed by a thermal oxidation method using dry oxygen.Type: GrantFiled: December 30, 2003Date of Patent: November 2, 2004Assignees: National Institute of Advanced Industrial Science and Technology, Japan Science and Technology Corporation, Sanyo Electric Co., Ltd.Inventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi, Seiji Suzuki
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Patent number: 6759684Abstract: An MIS transistor that uses a silicon carbide substrate has a buried channel structure. The surface orientation of the silicon carbide substrate is optimized so that the device does not assume a normally on state, has good hot-carrier endurance and punch-through endurance, and high channel mobility. In particular, a P-type silicon carbide semiconductor substrate is used to form a buried channel region. To achieve high mobility, the depth at which the buried channel region is formed is optimized, and the ratio between buried channel region junction depth (Lbc) source and drain region junction depth (Xj) is made to be within 0.2 to 1.0. The device can be formed on any surface of a hexagonal or rhombohedral or a (110) surface of a cubic system silicon carbide crystal, and provides a particularly good effect when formed on the (11-20) surface.Type: GrantFiled: November 14, 2001Date of Patent: July 6, 2004Assignees: National Institute of Advanced Industrial Science and Technology, Japan Science and Technology CorporationInventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi
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Publication number: 20040087093Abstract: In a semiconductor device using a silicon carbide substrate (1), the object of the present invention is to provide a method of manufacturing a semiconductor device that is a buried channel region type transistor having hot-carrier resistance, high punch-through resistance and high channel mobility. This is achieved by using a method of manufacturing a buried channel type transistor using a P-type silicon carbide substrate that includes a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer. The gate insulation layer is formed by a thermal oxidation method using dry oxygen.Type: ApplicationFiled: December 30, 2003Publication date: May 6, 2004Inventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi, Seiji Suzuki
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Publication number: 20030231628Abstract: A routing device includes a memory for storing routing entries in a routing table and a cache memory for storing some of routing entries present in the memory together with information of a mask length of a destination address as a cache entry. A high-speed retrieval section retrieves the cache entry corresponding to the destination address as referencing the cache memory based on the destination address of an input packet. An ordinary retrieval section retrieves the routing entry corresponding to the destination address as referencing the memory. A caching processing section writes the cache entry into the cache memory based on the routing entry retrieved by the ordinary retrieval section. The router device enables routing without using a routing entry that should not be used in the routing originally even when part of the routing table is cached as well as suppressing usage quantity of the cache entries to improve their usage efficiency.Type: ApplicationFiled: June 17, 2003Publication date: December 18, 2003Applicant: NEC CORPORATIONInventors: Shinsuke Harada, Takeharu Yasuda
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Publication number: 20020047125Abstract: An MIS transistor that uses a silicon carbide substrate has a buried channel structure. The surface orientation of the silicon carbide substrate is optimized so that the device does not assume a normally on state, has good hot-carrier endurance and punch-through endurance, and high channel mobility. In particular, a P-type silicon carbide semiconductor substrate is used to form a buried channel region. To achieve high mobility, the depth at which the buried channel region is formed is optimized, and the ratio between buried channel region junction depth (Lbc) source and drain region junction depth (Xj) is made to be within 0.2 to 1.0. The device can be formed on any surface of a hexagonal or rhombohedral or a (110) surface of a cubic system silicon carbide crystal, and provides a particularly good effect when formed on the (11-20) surface.Type: ApplicationFiled: November 14, 2001Publication date: April 25, 2002Applicant: Nat ' l Inst. of Advanced industrial and TechnologyInventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi