Abstract: A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.

Abstract: A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.

Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.

Abstract: A silicon carbide semiconductor device has a first-conductivity-type semiconductor layer having a lower impurity concentration and formed on a first-conductivity-type semiconductor substrate, a second-conductivity-type semiconductor layer having a higher impurity concentration and selectively formed in the first-conductivity-type semiconductor layer, a second-conductivity-type base layer having a lower impurity concentration formed on a surface of the second-conductivity-type semiconductor layer, a first-conductivity-type source region selectively formed in a surface layer of the base layer, a first-conductivity-type well region formed to penetrate the base layer from a surface to the first-conductivity-type semiconductor layer, and a gate electrode formed via a gate insulation film on a surface of the base layer interposed between the source region and the well region.

Abstract: In a front surface of a semiconductor base body, a gate trench is disposed penetrating an n+-type source region and a p-type base region to a second n-type drift region. In the second n-type drift region, a p-type semiconductor region is selectively disposed. Between adjacent gate trenches, a contact trench is disposed penetrating the n+-type source region and the p-type base region, and going through the second n-type drift region to the p-type semiconductor region. A source electrode embedded in the contact trench contacts the p-type semiconductor region at a bottom portion and corner portion of the contact trench, and forms a Schottky junction with the second n-type drift region at a side wall of the contact trench.

Abstract: In a front surface of a semiconductor base body, a gate trench is disposed penetrating an n+-type source region and a p-type base region to a second n-type drift region. In the second n-type drift region, a p-type semiconductor region is selectively disposed. Between adjacent gate trenches, a contact trench is disposed penetrating the n+-type source region and the p-type base region, and going through the second n-type drift region to the p-type semiconductor region. A source electrode embedded in the contact trench contacts the p-type semiconductor region at a bottom portion and corner portion of the contact trench, and forms a Schottky junction with the second n-type drift region at a side wall of the contact trench.

Abstract: A method of evaluating a semiconductor device having an insulated gate formed of a metal-oxide film semiconductor. The semiconductor device has a high potential side and a low potential side, and a threshold voltage that is a minimum voltage for forming a conducting path between the high and low potential sides. The method includes determining a variation of the threshold voltage at turn-on of the semiconductor device by continuously applying an alternating current (AC) voltage to the gate of the semiconductor device, a maximum voltage of the AC voltage being equal to or higher than the threshold voltage of the semiconductor device.

Abstract: In an active region, p+ regions are selectively disposed in a surface layer of an n? drift layer on an n+ semiconductor substrate. A p-base layer is disposed on surfaces of the n? drift layer and the P+ regions, and an MOS structure is disposed on the p-base layer. In another portion of the active region, a p+ region is disposed to be in contact with the source electrode on the p+ regions. In a breakdown voltage structure region (100), a JTE structure having at least a P? region is disposed separately from the P+ regions and the p-base layer, to surround the active region. The P? region is electrically in contact with the P+ region in a portion in which the MOS structure is not formed, in the vicinity of the boundary between the active region and the breakdown voltage structure region.

Abstract: A base layer is used that has an N-type SiC layer formed in a surface layer on the front surface side of an N-type SiC substrate, and a P-type region is formed on a surface of the N-type SiC layer with an N-type source region selectively formed in a surface layer of the P-type region. A source electrode is formed on a surface of the N-type source region and a drain electrode is formed on the back surface side of the N-type SiC substrate. Additionally, the gate electrode is formed via a gate insulation film only on a surface of the P-type region. In this way, high electric field is no longer applied to the gate insulation film on the surface of the N-type SiC layer due to stoppage of voltage application to the gate electrode.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming on a front surface of a silicon carbide substrate of a first conductivity type, a silicon carbide layer of the first conductivity type of a lower concentration; selectively forming a region of a second conductivity type in a surface portion of the silicon carbide layer; selectively forming a source region of the first conductivity type in the region; forming a source electrode electrically connected to the source region; forming a gate insulating film on a surface of the region between the silicon carbide layer and the source region; forming a gate electrode on the gate insulating film; forming a drain electrode on a rear surface of the substrate; forming metal wiring comprising aluminum for the device, the metal wiring being connected to the source electrode; and performing low temperature nitrogen annealing after the metal wiring is formed.

Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage is provided. For this, a first deposition film (2) of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate (1) of a first conductivity type. Formed on the first deposition film (2) is a second deposition film (31) that comprises a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film (32) formed on the second deposition film, which comprises a second region that is wider than the selectively removed first region, a high concentration source region (5) of a first conductivity type and a low concentration gate region (11) of a second conductivity type. A low concentration base region (4) of a first conductivity type is formed in contact with the first deposition film (2) in the first and second regions.

Abstract: A vertical high voltage semiconductor apparatus includes a first conductivity semiconductor substrate; a first conductivity semiconductor layer disposed on the semiconductor substrate and having an impurity concentration lower than the semiconductor substrate; a second conductivity semiconductor layer disposed on the first conductivity semiconductor layer; a second conductivity base layer disposed on the first conductivity semiconductor layer and the second conductivity semiconductor layer and, having an impurity concentration lower than the second conductivity semiconductor layer; and a first conductivity source region selectively disposed inside the base layer.

Abstract: In forming an ohmic electrode on a back surface of an n-type SiC substrate, an n+-type semiconductor region is formed in a surface layer of the back surface of an n-type epitaxial substrate by ion implantation. In this ion implantation, the impurity concentration of the n+-type semiconductor region is a predetermined range and preferably a predetermined value or less, and an n-type impurity is implanted by acceleration energy of a predetermined range such that the n+-type semiconductor region has a predetermined thickness or less. Thereafter, a nickel layer and a titanium layer are sequentially formed on the surface of the n+-type semiconductor region, the nickel layer is heat treated to form a silicide, and the ohmic electrode formed from nickel silicide is formed. In this manner, a back surface electrode that has favorable properties can be formed while peeling of the back surface electrode can be suppressed.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a second electrode, a control electrode and an insulating film. The first semiconductor region is of a first conductivity type and includes SiC. The second semiconductor region is provided on the first semiconductor region and has a first surface. The second semiconductor region is of a second conductivity type and includes SiC. The third semiconductor region is provided on the second semiconductor region, is of the first conductivity type and includes SiC. The first and second electrodes are electrically connected to the third semiconductor region. The control electrode is provided on the second semiconductor region. The insulating film is provided between the second semiconductor region and the control electrode. The insulating film contacts the first surface and the control electrode and includes nitrogen.

Abstract: An infrared ray absorbing film is selectively formed on a surface of a silicon carbide semiconductor substrate in a predetermined area. An aluminum film and a nickel film are sequentially formed in this order on the silicon carbide semiconductor substrate in an area excluding the predetermined area in which the infrared ray absorbing film is formed. The silicon carbide semiconductor substrate is thereafter heated using a rapid annealing process with a predetermined heating rate to form an electrode. The rapid annealing process converts the nickel film into a silicide and, with the aluminum film, provides an electrode having ohmic contact.

Abstract: To provide a vertical SIC-MOSFET and IGBT capable of having low ON-resistance without destruction of gate oxide films or degradation of reliability even when a high voltage is applied, and a fabrication method thereof, a vertical mosfet has a semiconductor layer and a base layer joined instead of a well region 6 so as to include, as a joining portion, a point that is farthest and equidistant from centers of all the source regions facing each other and that is closest and equidistant from end portions farthest from the centers of the source regions in a planar view.

Abstract: In an embodiment, on an n?type SiC layer on an n+-type SiC semiconductor substrate and a p+ layer selectively formed on the n?type SiC layer, a p base layer is formed on which, a p+ contact layer is selectively formed. From a surface, an n counter layer penetrates the p base layer to the n?type SiC layer. A gate electrode layer is disposed via a gate insulating film, on an exposed surface of the p base layer between the p+ contact layer and the n counter layer; and a source electrode contacts the p+ contact layer and the p base layer. In a back surface, a drain electrode is disposed. A portion of the p+ layers are joined at a region of a drain electrode side of the n counter layer, by a joining unit and a p+ layer contacts a drain electrode side of the p+ layer.

Abstract: An n-type SiC layer is formed on a front face of an n+-type SiC substrate and plural p-type regions are selectively formed inside the n-type SiC layer. A p-type SiC layer is formed covering the surfaces of the n-type SiC layer and the p-type regions. An n-type region is formed inside the p-type SiC layer to be connected to the n-type SiC layer. An n+-type source region and a p+-type contact region are formed inside the p-type SiC layer, positioned away from the n-type region and in contact with each other. The n-type region in the p-type SiC layer is formed such that the width LJFET of the n-type region is within a range from 0.8 ?m to 3.0 ?m and the impurity concentration of the n-type region is greater than 1.0×1016 cm?3 and less than or equal to 5.0×1016 cm?3.

Abstract: A vertical high voltage semiconductor apparatus includes a first conductivity semiconductor substrate; a first conductivity semiconductor layer disposed on the semiconductor substrate and having an impurity concentration lower than the semiconductor substrate; a second conductivity semiconductor layer disposed on the first conductivity semiconductor layer; a second conductivity base layer disposed on the first conductivity semiconductor layer and the second conductivity semiconductor layer and, having an impurity concentration lower than the second conductivity semiconductor layer; and a first conductivity source region selectively disposed inside the base layer.

Abstract: A silicon carbide vertical field effect transistor includes a first-conductive-type silicon carbide substrate; a low-concentration first-conductive-type silicon carbide layer formed on a surface of the first-conductive-type silicon carbide substrate; second-conductive-type regions selectively formed on a surface of the first-conductive-type silicon carbide layer; first-conductive-type source regions formed in the second-conductive-type regions; a high-concentration second-conductive-type region formed between the first-conductive-type source regions in the second-conductive-type region; a source electrode electrically connected to the high-concentration second-conductive-type region and a first-conductive-type source region; a gate insulating film formed from the first-conductive-type source regions formed in adjacent second-conductive-type regions, onto the second-conductive-type regions and the first-conductive-type silicon carbide layer; a gate electrode formed on the gate insulating film; and a drain elec