Abstract: A vertical MOSFET of a trench gate structure includes an n?-type drift layer and a p+-type base layer formed by epitaxial growth. The vertical MOSFET includes a trench that penetrates the n?-type drift layer and the p+-type base layer. A low-concentration thin film is provided in the trench. The low-concentration thin film is in contact with the p+-type base layer and is of the same conductivity type as the p+-type base layer. Further, the low-concentration thin film has an impurity concentration that is lower than that of the p+-type base layer.

Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.

Abstract: In an embodiment, on an n?type SiC layer on an n+-type SiC semiconductor substrate and a p+ layer selectively formed on the n?type SiC layer, a p base layer is formed on which, a p+ contact layer is selectively formed. From a surface, an n counter layer penetrates the p base layer to the n?type SiC layer. A gate electrode layer is disposed via a gate insulating film, on an exposed surface of the p base layer between the p+ contact layer and the n counter layer; and a source electrode contacts the p+ contact layer and the p base layer. In a back surface, a drain electrode is disposed. A portion of the p+ layers are joined at a region of a drain electrode side of the n counter layer, by a joining unit and a p+ layer contacts a drain electrode side of the p+ layer.

Abstract: At bottom of a gate trench, a conductive layer is provided. A Schottky junction is formed along a side wall of the gate trench by the conductive layer and the n-type current spreading region. The Schottky junction constitutes one unit cell of a trench-type SBD. In the gate trench, a gate electrode is provided on the conductive layer, via an insulating layer. The gate electrode constitutes one unit cell of a trench-gate-type vertical MOSFET. In other words, one unit cell of the trench gate MOSFET and one unit cell of the trench-type SBD are disposed built into a single gate trench and oppose each other in a depth direction.

Abstract: Plural trenches are provided in a semiconductor substrate. First p+-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p+-type regions disposed in a MOS cell region C? that is substantially half of a region between the adjacent second trenches is in a range of about 2 ?m to 8 ?m.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes first, second, and third electrode regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. The first partial region is separated from the first electrode. The second partial region is separated from the first electrode region. The fourth partial region is separated from the second electrode region. The second semiconductor region includes sixth, seventh, eighth and ninth partial regions. The third semiconductor region is connected to the second semiconductor region. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes tenth, eleventh, and twelfth partial regions. The first insulating film is provided between the first, third, and fourth semiconductor regions.

Abstract: According to one embodiment, a semiconductor device includes a first conductive portion, a semiconductor portion including silicon carbide, and a first insulating portion. The semiconductor portion includes first to fourth semiconductor regions. The first semiconductor region includes first and second partial regions. The third semiconductor region is provided between the second partial region and the second semiconductor region. The fourth semiconductor region is provided between the first conductive portion and the first partial region. The first insulating portion includes first to third portions. A portion of the first portion is positioned between the first conductive portion and the fourth semiconductor region. The second portion is positioned between the second semiconductor region and the portion of the first conductive portion and between the first conductive portion and the third semiconductor region. The third portion is provided between the first and second portions.

Abstract: In an n-type current diffusion region, a first p+-type region is provided under a bottom of a trench (gate trench). Further, in the n-type current diffusion region, a second p+-type region is provided between adjacent trenches so as to be separated from the first p+-type region and in contact with a p-type base region. In the p-type base region, a third p+-type region is provided near a side wall of the trench so as to be separated from the trench and first and second p+-type regions. A depth of the third p+-type region from an interface of the p-type base region and an n+-type source region does not reach the n-type current diffusion region. A shortest distance from the third p+-type region to the second p+-type region is at most a distance between the first and second p+-type regions.

Abstract: In an n-type current diffusion region, a first p30-type region underlying a bottom of a trench (gate trench) is provided. In the n-type current diffusion region, a second p30-type region is provided between adjacent trenches, separated from the first p30-type region and in contact with the p-type base region. In the p-type base region, near a side wall of the trench, a third p30-type region is provided a predetermined distance from the side wall of the trench and is separated from the first and the second p30-type regions. The third p30-type region extends in a depth direction, substantially parallel to the side wall of the trench. A drain-side end of the third p30-type region is in contact with the n-type current diffusion region or protrudes a predetermined depth from the interface of the p-type base region and the n-type current diffusion region toward the drain.

Abstract: A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.

Abstract: In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction. An end (toward a drain electrode) of the second base region of the second conductivity type, and an end (toward the drain electrode) of a first base region of the second conductivity type reach a position deeper than an end (toward the drain electrode) of a region of a first conductivity type. Thus, the electric field at a gate insulating film at the trench bottom is mitigated, suppressing the breakdown voltage of the active region and enabling breakdown voltage design of the edge termination region to be facilitated. Further, such a semiconductor device may be formed by an easy method of manufacturing.

Abstract: On a front surface of a semiconductor base, a first n?-type drift region, a second n-type drift region, and a third n+-type drift region are provided. In the front surface of the semiconductor base, a gate trench is provided penetrating the n+-type source region and the p-type base region, and reaching the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region, the p-type base region, and the second and third n-type drift regions, and that reaches the p-type semiconductor region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at the bottom and the corners of the contact trench and forms a Schottky junction with the third n+-type drift region and the second n-type drift region at a side wall of the contact trench.

Abstract: A semiconductor device includes an n-type silicon carbide epitaxial layer on a front surface of an n+-type silicon carbide substrate. A first p+-type base region is provided in the n-type silicon carbide epitaxial layer and a breakdown voltage structure region is provided in an outer periphery of an active region through which a main current flows. A distance between the first p+-type base region and a front surface of the n+-type silicon carbide substrate is smaller than a distance between the breakdown voltage structure region and the front surface of the n+-type silicon carbide substrate.

Abstract: At a front surface of a silicon carbide base, an n?-type drift layer, a p-type base layer, a first n+-type source region, a second n+-type source region, and a trench that penetrates the first and the second n+-type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided on the gate electrode, and a barrier metal is provided on the interlayer insulating film.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, an upper second p+-type region, a lower second p+-type region and a first p+-type region are provided. The lower second p+-type region is provided orthogonal to a trench, and a total mathematical area regions that are between the first p+-type region and the p-type base layer and that include the n-type region is at least two times a total mathematical area of regions that are between the first p+-type region and the p-type base layer and that include the upper second p+-type region.

Abstract: On a front surface of a semiconductor base, a first n?-type drift region and a second n-type drift region are provided. A gate trench is provided that penetrates an n+-type source region and p-type base region, and reaches the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region and the p-type base region, and reaches a p-type semiconductor region, through the second n-type drift region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at a bottom and corners of the contact trench, and forms a Schottky junction with the second n-type drift region at side walls of the contact trench. A depth of the contact trench is a depth by which a mathematical area of a part thereof forming the Schottky junction is a predetermined mathematical area or greater.

Abstract: On a surface of an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate, first and second p+-type base regions are formed in the n-type silicon carbide epitaxial layer, an n-type region is formed in the n-type silicon carbide epitaxial layer, a p-type base layer is formed on the n-type region, an n+-type source region and a p++-type contact region are formed in the p-type base layer, and a trench is formed to a position shallower than the second p+-type base region and penetrates the p-type base layer. A first sidewall angle of the trench at a position of the p-type base layer is 80° to 90° with respect to a main surface. A difference of the first sidewall angle and a second sidewall angle of the trench at a position deeper than a boundary of the p-type base layer and the n-type region is 1° to 25°.

Abstract: On a front surface of a semiconductor base, an n?-type drift layer, a p-type base layer, an n++-type source region, and a gate trench and a contact trench penetrating the n++-type source region and the p-type base layer and reaching the n?-type drift layer are provided. The contact trench is provided separated from the gate trench. A Schottky metal is embedded in the contact trench and forms a Schottky contact with the n?-type drift layer at a side wall of the contact trench. An ohmic metal is provided at a bottom of the contact trench and forms an ohmic contact with the n?-type drift layer.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming on a front surface of a silicon carbide substrate of a first conductivity type, a silicon carbide layer of the first conductivity type of a lower concentration; selectively forming a region of a second conductivity type in a surface portion of the silicon carbide layer; selectively forming a source region of the first conductivity type in the region; forming a source electrode electrically connected to the source region; forming a gate insulating film on a surface of the region between the silicon carbide layer and the source region; forming a gate electrode on the gate insulating film; forming a drain electrode on a rear surface of the substrate; forming metal wiring comprising aluminum for the device, the metal wiring being connected to the source electrode; and performing low temperature nitrogen annealing after the metal wiring is formed.

Abstract: A method of evaluating a semiconductor device having an insulated gate formed of a metal-oxide film semiconductor. The semiconductor device has a high potential side and a low potential side, and a threshold voltage that is a minimum voltage for forming a conducting path between the high and low potential sides. The method includes determining a variation of the threshold voltage at turn-on of the semiconductor device by continuously applying an alternating current (AC) voltage to the gate of the semiconductor device, a maximum voltage of the AC voltage being equal to or higher than the threshold voltage of the semiconductor device.