Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.

Abstract: An active region through which current flows in a semiconductor device includes an n?-type silicon carbide epitaxial layer formed on a front surface of an n+-type silicon carbide semiconductor substrate; a p-type layer becoming a channel region; a trench formed so as to be in contact with a p-type layer and having an oxide film and a gate electrode embedded therein; a p+-type layer arranged beneath the trench and between trenches; an n?-type layer in contact with the p-type layer, a p+-type layer, and the trench, and arranged in contact with a p+-type layer or on a surface side of the semiconductor substrate; an n-type layer in contact with the n?-type silicon carbide epitaxial layer and the p+-type layer, and having an impurity concentration higher than that of the n?-type layer and that of the n?-type silicon carbide epitaxial layer.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes first, second, and third electrode regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. The first partial region is separated from the first electrode. The second partial region is separated from the first electrode region. The fourth partial region is separated from the second electrode region. The second semiconductor region includes sixth, seventh, eighth and ninth partial regions. The third semiconductor region is connected to the second semiconductor region. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes tenth, eleventh, and twelfth partial regions. The first insulating film is provided between the first, third, and fourth semiconductor regions.

Abstract: In an active region, a contact trench in which a source electrode is embedded is provided. In a boundary region between the active region and the edge termination region, a tapered trench is provided. A second p-type base region is provided along an inner wall of the contact trench and extends to the boundary region to be provided along a base front surface and an inner wall of the tapered trench. An angle ?3 of the side walls of the tapered trench with respect to a substrate front surface is smaller than an angle ?1 of the side walls of the contact trench with respect to the substrate front surface. At a second mesa portion between the tapered trench and a step of the edge termination region, a gate runner is arranged on the base front surface, via a field oxide film.

Abstract: In a semiconductor device having a first p+-type base region, a second p+-type base region, a high-concentration n-type region selectively formed in an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate; a p-type base layer formed on the n-type silicon carbide epitaxial layer; an n+-type source region and a p++-type contact region selectively formed in a surface layer of the p-type base layer; and a trench formed penetrating the p-type base layer and shallower than the second p+-type base region, in at least a part of the first p+-type base region, a region is shallower than the second p+-type base region as viewed from an element front surface side.

Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.

Abstract: In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction. An end (toward a drain electrode) of the second base region of the second conductivity type, and an end (toward the drain electrode) of a first base region of the second conductivity type reach a position deeper than an end (toward the drain electrode) of a region of a first conductivity type. Thus, the electric field at a gate insulating film at the trench bottom is mitigated, suppressing the breakdown voltage of the active region and enabling breakdown voltage design of the edge termination region to be facilitated. Further, such a semiconductor device may be formed by an easy method of manufacturing.

Abstract: A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction. A longitudinal direction of the trench, which is perpendicular to the depth direction, is parallel to the off-direction of the silicon carbide substrate.

Abstract: A p-type base region is constituted by first to fifth p-type base regions. The first p-type base region is provided deeper than gate trenches. The second p+-type base region is provided along side walls of a contact trench. The fourth p+-type base region is provided along a bottom of the contact trench and is exposed at the bottom of the contact trench. The fifth p-type base region is in contact with the second and fourth p+-type base regions, which have an impurity concentration higher than that of the fifth p-type base region. The fifth p-type base region is provided along the bottom of the contact trench and deeper than the fourth p+-type base region. In the fifth p-type base region, the third p++-type base region, which has an impurity concentration higher than that of the fifth p-type base region, is arranged.

Abstract: On a front surface of a semiconductor base, a first n?-type drift region, a second n-type drift region, and a third n+-type drift region are provided. In the front surface of the semiconductor base, a gate trench is provided penetrating the n+-type source region and the p-type base region, and reaching the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region, the p-type base region, and the second and third n-type drift regions, and that reaches the p-type semiconductor region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at the bottom and the corners of the contact trench and forms a Schottky junction with the third n+-type drift region and the second n-type drift region at a side wall of the contact trench.

Abstract: In an active region, a contact trench in which a source electrode is embedded is provided. In a boundary region between the active region and the edge termination region, a tapered trench is provided. A second p-type base region is provided along an inner wall of the contact trench and extends to the boundary region to be provided along a base front surface and an inner wall of the tapered trench. An angle ?3 of the side walls of the tapered trench with respect to a substrate front surface is smaller than an angle ?1 of the side walls of the contact trench with respect to the substrate front surface. At a second mesa portion between the tapered trench and a step of the edge termination region, a gate runner is arranged on the base front surface, via a field oxide film.

Abstract: Each first p+-type region is provided between adjacent trenches embedded with a MOS gate and is in contact with a p-type base region. Second p+-type regions face a bottom and bottom corner portions of the trenches in a depth direction. An n-type CS region is a current spread layer provided between the first p+-type regions and the second p+-type regions. The n-type CS region is provided only in an active region and an end thereof is positioned at a boundary of the active region and an edge termination region. Further, the n-type CS region extends to be flush with or farther inward than an outermost first p+-type region. An outermost p++-type contact region extends from a drop between the active region and the edge termination region to the edge termination region and extends beyond the n-type CS region.

Abstract: Each first p+-type region is provided between adjacent trenches embedded with a MOS gate and is in contact with a p-type base region. Second p+-type regions face a bottom and bottom corner portions of the trenches in a depth direction. An n-type CS region is a current spread layer provided between the first p+-type regions and the second p+-type regions. The n-type CS region is provided only in an active region and an end thereof is positioned at a boundary of the active region and an edge termination region. Further, the n-type CS region extends to be flush with or farther inward than an outermost first p+-type region. An outermost p++-type contact region extends from a drop between the active region and the edge termination region to the edge termination region and extends beyond the n-type CS region.

Abstract: A vertical MOSFET of a trench gate structure includes an n?-type drift layer and a p+-type base layer formed by epitaxial growth. The vertical MOSFET includes a trench that penetrates the n?-type drift layer and the p+-type base layer. A low-concentration thin film is provided in the trench. The low-concentration thin film is in contact with the p+-type base layer and is of the same conductivity type as the p+-type base layer. Further, the low-concentration thin film has an impurity concentration that is lower than that of the p+-type base layer.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a second electrode, a control electrode and an insulating film. The first semiconductor region is of a first conductivity type and includes SiC. The second semiconductor region is provided on the first semiconductor region and has a first surface. The second semiconductor region is of a second conductivity type and includes SiC. The third semiconductor region is provided on the second semiconductor region, is of the first conductivity type and includes SiC. The first and second electrodes are electrically connected to the third semiconductor region. The control electrode is provided on the second semiconductor region. The insulating film is provided between the second semiconductor region and the control electrode. The insulating film contacts the first surface and the control electrode and includes nitrogen.

Abstract: A silicon carbide semiconductor element includes n-type silicon carbide epitaxial layers formed on an n+-type silicon carbide semiconductor substrate, plural p base layers selectively formed in surfaces of the silicon carbide epitaxial layers, a p-type silicon carbide epitaxial layer formed in the silicon carbide epitaxial layer, and a trench penetrating at least the silicon carbide epitaxial layer. The silicon carbide semiconductor element also includes, in a portion of the silicon carbide epitaxial layer, a mesa portion exposing the p base layer. The silicon carbide semiconductor element further includes, between consecutive mesa side faces of the mesa portion, a flat portion substantially parallel to the silicon carbide substrate. The remaining thickness of the exposed p base layer is larger than 0.5 ?m and smaller than 1.0 ?m.

Abstract: An infrared ray absorbing film is selectively formed on a surface of a silicon carbide semiconductor substrate in a predetermined area. The infrared ray absorbing film is composed of one of a multi-layered film of titanium nitride and titanium, a multi-layered film of molybdenum nitride and molybdenum, a multi-layered film of tungsten nitride and tungsten, or a multi-layered film of chromium nitride and chromium. An aluminum film and a nickel film are sequentially formed in this order on the silicon carbide semiconductor substrate in an area excluding the predetermined area in which the infrared ray absorbing film is formed. The silicon carbide semiconductor substrate is thereafter heated using a rapid annealing process with a predetermined heating rate to form an electrode. The rapid annealing process converts the nickel film into a silicide and, with the aluminum film, provides an electrode having ohmic contact.

Abstract: An active region through which current flows in a semiconductor device includes an n?-type silicon carbide epitaxial layer formed on a front surface of an n+-type silicon carbide semiconductor substrate; a p-type layer becoming a channel region; a trench formed so as to be in contact with a p-type layer and having an oxide film and a gate electrode embedded therein; a p+-type layer arranged beneath the trench and between trenches; an n?-type layer in contact with the p-type layer, a p+-type layer, and the trench, and arranged in contact with a p+-type layer or on a surface side of the semiconductor substrate; an n-type layer in contact with the n?-type silicon carbide epitaxial layer and the p+-type layer, and having an impurity concentration higher than that of the n?-type layer and that of the n?-type silicon carbide epitaxial layer.

Abstract: A semiconductor device includes in an active region in which current flows, an n+-type silicon carbide epitaxial layer of a low concentration and formed on an n+-type silicon carbide substrate; a p-type channel region constituting a channel region; a trench contacting the p-type channel region and having embedded therein an oxide film and a gate electrode; a p+-type base layer arranged beneath the trench; a third n-type CSL layer region contacting the p-type channel region; a second n-type CSL layer region having a maximum impurity concentration higher than that of the third n-type CSL layer region, the maximum impurity concentration being farther on a substrate front side than a top of the p+-type base layer arranged beneath the trench is; and a first n-type CSL layer region contacting the second n-type CSL layer region and having a maximum impurity concentration lower than that of the second n-type CSL layer region.

Abstract: An information processing system includes circuitry that receives position information of first stroke information and second stroke information drawn on a display at different timing, adds additional information indicating a relationship of the received first stroke information and the received second stroke information to the received first stroke information, and generates, based on the position information of the received first stroke information, the position information of the received second stroke information and the added additional information, consecutive data used for displaying (playing) information drawn on the display as the first stroke information and the second stroke information, and a memory that stores the generated consecutive data.