Abstract: The semiconductor relay comprises: an insulated type DC/DC power supply 10 having the input terminal and the output terminal insulated from each other; a pulse transformer 20 having the input terminal and the output terminal insulated from each other; an analog switch 30 which turns on and off the circuit in accordance with a state of an input signal; and a MOSFET circuit 40 which turns on and off a high voltage to a load 50. When a pulse signal is outputted from a pulse signal source 28, the pulse signal is outputted from the pulse transformer 20, and a state of the analog switch 30 is switched, a supply voltage is outputted from the output terminal of the analog switch 30, both the MOSFETs 42, 44 of the MOSFET circuit conduct, and a high AC voltage is applied to a load 50 from an AC power supply 52.

Abstract: The present invention aims to eliminate the mounting of an independent ammonia oxidation catalyst to an exhaust passage. A selective reduction catalyst comprises a catalyst support 23 in which a plurality of through holes 23b partitioned by porous walls 23a are formed and a first active component 24 carried by the walls which dissolves nitrogen oxide contained in the exhaust gas by the reaction with ammonia. Inlet portions 23c and outlet portions 23d, adjacent to each other, of the plurality of through holes 23b are alternately sealed, and the wall 23a carrying the first active component 24 has ventilation and a second active component 26 having a catalytic action so as to oxidize ammonia having passed the wall is carried on the inner surface of the though hole.

Abstract: The present invention aims to effectively prevent NOx from being emitted into the atmosphere even if the temperature of exhaust gas is relatively low. A selective reduction catalyst comprises a catalyst support 26 in which a plurality of through holes partitioned by porous walls are formed in parallel with each other and an active component having a catalytic action and carried by the walls. Inlet portions and outlet portions, adjacent to each other, of the through holes are alternately sealed, and the wall carrying the active component is formed so that a particle-state solid matter ammonium nitrate cannot pass through it.

Abstract: A driver for supplying a test signal to a device under test is shared by a plurality of terminals. In this way, the cost and time required for the test of the device under test can be reduced. A testing apparatus 10 relating to the present invention includes a test signal generating section 130 that generates a test signal to be supplied to a device under test 20, a driver 140 that outputs the test signal, a switch 150 that is disposed on a wire between the driver 140 and a first terminal of the device under test 20, a switch 160 that is disposed on a wire between the driver 140 and a second terminal of the device under test 20, and a connection control section 100 that (i) turns on the switch 150 and turns off the switch 160 when the test signal is supplied to the first terminal of the device under test 20, and (ii) turns off the switch 150 and turns on the switch 160 when the test signal is supplied to the second terminal of the device under test 20.

Abstract: A multi-strobe generation apparatus for generating a multi-strobe has a plurality of strobes. The multi-strobe generation apparatus includes a shift clock generating section which outputs a shift clock generated by dividing a reference clock at a timing at which each strobe is generated, a strobe generating section for generating the multi-strobe corresponding to each leading or trailing edge of the reference clock, and an adjustment section for adjusting timing at which the strobe generating section generates each strobe based on the shift clock.

Abstract: This magnetic recording medium has a substrate, a nonmagnetic granular layer formed above the substrate and a recording layer formed on the nonmagnetic granular layer. The nonmagnetic granular layer is made of CoCr alloy with an hcp or an fcc crystal structure in which a nonmagnetic material segregates virtually-columnar magnetic grains. The magnetic recording medium and the magnetic storage apparatus in which the medium is used have improved reading/writing performances.

Abstract: There is provided a test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, having a logical comparator for comparing each data contained in the data string read out of the memory-under-test with an expected value generated in advance, a data error counting section for counting a number of data inconsistent with the expected value, a plurality of registers, provided corresponding to each of a plurality of classes, for storing an upper limit value of a number of errors contained in the data -under-test to be classified into the class, comparing sections for comparing each of the plurality of upper limit values stored in the plurality of registers with the counted value of the data error counting section and a classifying section for classifying the memory-under-test into the class corresponding to the register storing the upper limit value which is greater than the counted value.

Abstract: A first electrode of a liquid crystal cell (21) is composed of a plurality of concentric electrodes (31 to 34) of a concentrically circular shape, the plurality of concentric electrodes are divided into a first group of concentric electrodes (44) near the center and a second group of concentric electrodes (45) near the periphery, and a concentric electrode between the two groups is an independent single electrode (36). A first correction unit that corrects spherical aberration of a high density DVD is composed of the two groups and a second correction unit that corrects aberration of a conventional DVD is composed of the first group of concentric electrodes (44). In the case of correcting the aberration of the conventional DVD, the independent concentric electrode (36) is supplied with a voltage between the voltages respectively supplied to adjacent concentric electrodes (35), (37).

Abstract: An interface circuit is provided between a first circuit block and a second circuit block that operates using a power supply system differing from that of the first circuit block. An electrostatic discharge protection circuit that include a PN diode and a diffused resistor is formed in order to prevent electrostatic discharge destruction of a gate insulating film of a transistor that forms the interface circuit. The electrostatic discharge protection circuit may be formed using the remaining basic cells of a gate array that forms the second circuit block. An electrostatic discharge protection circuit formed of a bidirectional diode may be connected between a first low-potential power supply and a second low-potential power supply.

Abstract: An integrated circuit device includes a first circuit block that includes low-voltage transistors (LVTr) and operates using a first high-potential power supply voltage and a first low-potential power supply voltage, a second circuit block that includes low-voltage transistors (LVTr) and operates using a second high-potential power supply voltage and a second low-potential power supply voltage that differ in power supply system from the first circuit block, and an interface circuit (I/O buffer) provided between the first circuit block and the second circuit block. The interface circuit (I/O buffer) includes medium-voltage transistors (MVTr: transistors of which the thickness of the gate insulating film is larger than that of the low-voltage transistors (LVTr)). An electrostatic discharge protection circuit formed of bidirectional diodes is provided between a first and second low-potential power supply nodes.

Abstract: The present invention provides a test apparatus that tests a plurality of memories under test. The test apparatus includes a data input-output section that gives and receives data to and from data input-output terminals of the plurality of memories under test, a test data supplying section that parallel supplies test data to the plurality of memories under test, a writing control section that parallel supplies a write enable signal to the plurality of memories under test, a reading control section that sequentially supplies a read enable signal to each of the plurality of memories under test, a comparing section that compares the test data sequentially read from the respective memories under test with an expected value, and a detecting section that detects, on condition that one test data is not identical with the expected value, a writing fail for the memory under test that outputs this test data.

Abstract: Provided is a test apparatus including: test signal supply sections supplying a test signal writing test data to the connected memory under test, to a terminal of the memory; terminal correspondence determination sections outputting a terminal unit determination result indicating whether test data from the connected terminal matches an expected value; a determination result selection section selecting, for each memory, terminal unit determination results from the terminal correspondence determination sections; a memory correspondence determination section determining whether writing succeeded to each memory, based on the selection result by the determination result selection section; an identifying section identifying a test signal supply section connected to the memory to which writing succeeded and a test signal supply section connected to the memory to which writing failed; and a mask treatment section instructing each test signal supply section whether to perform re-testing, according to whether writing s

Abstract: It is an object of the test apparatus according to the present invention to effectively manage test results.

Abstract: A multi-strobe apparatus for generating multi-strobe having a plurality of strobes is provided, wherein the multi-strobe apparatus includes a clock generating unit which is able to generate a signal for adjustment at a timing at which each of the plurality of strobes should be generated; a strobe generating circuit for generating the plurality of strobes; and an adjusting module for adjusting a timing of the strobe generating circuit's generating each of the strobes on the basis of the signal for adjustment.

Abstract: A gas barrier film, a display substrate and a display using the gas barrier film. The gas barrier film includes a base material film having a deflection temperature under load of 150° C. or above, and at least a gas barrier layer and a smoothing layer in that order, or a smoothing layer and a gas barrier layer in that order provided on the base material film. Preferably, the base material film is polyethylene naphthalate, the gas barrier layer is formed of an inorganic oxide, an inorganic oxynitride, an inorganic oxycarbide, or an inorganic oxycarbonitride, and the smoothing layer formed of a cardo polymer, sol-gel, or a material containing an acryl structure.

Abstract: A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail memory unit includes a write time measuring section for measuring a write time required for writing said test data per each of said pages, an integrating section for integrating said write time across a plurality of said pages set in advance, and a judging section for judging whether or not said memory-under-test is defect-free by comparing a value integrated by said integrating section with an expected value set in advance. The integrating section further integrates said write time per page group having said predetermined number of pages. The judging section further judges whether or not said page group is defect-free based on an integral value of said write time per said page group.

Abstract: A testing device that tests an electronic device includes a test pattern outputting unit operable to output a test pattern to the electronic device, a deciding unit operable to decide whether an output signal from the electronic device satisfies a predetermined condition, an instruction storing unit operable to store a plurality of instruction codes, a first instruction pipeline operable to generate a condition satisfaction instruction stream including a plurality of instructions that causes the test pattern outputting unit to output the test pattern to be supplied to the electronic device when the output signal satisfies the condition based on the plurality of instruction codes, a second instruction pipeline operable to generate a condition non-satisfaction instruction stream including a plurality of instructions that causes the test pattern outputting unit to output the test pattern to be supplied to the electronic device when the output signal does not satisfy the condition based on the plurality of instru

Abstract: When a throttle is fully open, a maximum torque set value is corrected based on the ratio between the maximum air volume set value under fully-open throttle conditions and the actual maximum air volume detected by an intake air volume meter such as an air flow sensor. Based on the corrected maximum torque set value, both the relation between the degree of accelerator opening and target torque and the relation between the target torque (target air volume) and the degree target throttle opening are corrected.

Abstract: A test apparatus compares bits included in a data sequence read from a DUT with expectation values. Comparison results are stored in a first failure memory (FM) as bit information indicating whether storage cells of the DUT are non-defective. The storage device counts the number of bits not matching the expectation values for each page, and judges for each grade/page of the DUT whether the number of bits not matching the expectation values meets the condition of that grade. Judgment results are stored in a second FM as page information indicating whether each page is non-defective for each grade. If page information of a page including a bit corresponding to a storage cell indicating that this page meets the condition of any grade is stored in the second FM, the apparatus outputs the bit information in the first FM, by changing it to a value indicating that storage cell is as non-defective.

Abstract: A test apparatus is provided for testing memory under test which stores a data string including an error correction code in the form of additional data. The test apparatus comprises: a logic comparator which compares each of the data sets included in a data string read out from the memory under test with a corresponding anticipated value created beforehand; a data error count unit which counts the number of data sets that do not match the respective anticipated values; and a defect detection unit which provides a function whereby, in a case that the count value counted by the error count unit exceeds a predetermined upper limit number which is equal to or greater than 1, determination is made that the memory under test is defective.