Abstract: A magnetic recording medium is disclosed that includes a substrate; and an underlayer, a first magnetic layer, a non-magnetic coupling layer, a second magnetic layer, a third magnetic layer, a non-magnetic separation layer, and a fourth magnetic layer stacked in this order on the substrate. The first magnetic layer and the second magnetic layer are antiferromagnetically exchange-coupled, and the second magnetic layer and the third magnetic layer are ferromagnetically exchange-coupled. The third magnetic layer has an anisotropic magnetic field smaller than the anisotropic magnetic field of the second magnetic layer, and has a saturation magnetization greater than the saturation magnetization of the second magnetic layer.

Abstract: Active temperature areas of selective reduction catalysts are expanded more than ever before so as to obtain high NOx reduction ratio in a larger exhaust temperature range. Disclosed is an exhaust emission control device with selective reduction catalyst incorporated in an exhaust pipe 9, the catalyst having enhanced reaction selectivity so as to selectively react NOx with ammonia even in the presence of oxygen, urea water 16 being added as reducing agent upstream of the catalyst by urea water adding means (urea water tank 13, urea water supply pipe 14, supply pump 15 and injection nozzle 17) so as to reduce and purify NOx. The catalyst comprises two or high- and low-temperature-active catalysts 11 and 12 with different active temperature areas. The catalysts are arranged in series in such a manner that the catalysts 11 and 12 with relatively high and low active temperature areas are positioned upstream and downstream, respectively.

Abstract: Excessive generation NO2 by oxidation catalyst arrangement upstream of a selective reduction catalyst is suppressed to prevent falling of NOx reduction rate. A selective reduction catalyst 4 capable of selectively reacting NOx with ammonia even in the presence of oxygen is incorporated in an exhaust pipe 3 from an engine 1. A pair of oxidation catalysts 5A and 5B are arranged in parallel with each other and upstream of the selective reduction catalyst. In an operation condition with low exhaust temperature, amounts of the exhaust gas 2 distributed to the oxidation catalysts 5A and 5B are adjusted so as to make NO/NO2 ratio in the exhaust gas 2 to about 1-1.5.

Abstract: An inventive test apparatus has a timing comparator for obtaining an output value of an output signal outputted from a memory-under-test with timing of a strobe signal, a logical comparator for comparing the output value obtained by the timing comparator with an expected value and for outputting a comparison result and a phase adjustment control circuit for adjusting the timing of the strobe signal based on the comparison result outputted from the logical comparator. The inventive test apparatus further includes a first variable delay circuit for delaying and supplying the strobe signal to the timing comparator and the phase adjustment control circuit sets the delay effected by the first variable delay circuit based on the comparison result outputted from the logical comparator.

Abstract: There is provided a testing apparatus for testing a memory-under-test, having a pin electronics section for inputting/receiving signals to/from the memory-under-test, a pattern generating section for inputting a test pattern to the memory-under-test via the pin electronics section and a judging section for receiving an output signal of the memory-under-test via the pin electronics section to judge whether or not the memory-under-test is defect-free based on the output signal, wherein the pin electronics section has an internal circuit for inputting/receiving the signal to/from the memory-under-test, a first transmission line for connecting the internal circuit with the memory-under-test and a first switch for connecting the first transmission line with earth potential when the memory-under-test is not tested and for disconnecting the first transmission line from the earth potential in testing the memory-under-test.

Abstract: There is provided a test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, having a logical comparator for comparing each data contained in the data string read out of the memory-under-test with an expected value generated in advance, a data error counting section for counting a number of data inconsistent with the expected value, a plurality of registers, provided corresponding to each of a plurality of classes, for storing an upper limit value of a number of errors contained in the data -under-test to be classified into the class, comparing sections for comparing each of the plurality of upper limit values stored in the plurality of registers with the counted value of the data error counting section and a classifying section for classifying the memory-under-test into the class corresponding to the register storing the upper limit value which is greater than the counted value.

Abstract: A testing apparatus for performing a setup testing or a hold testing on a device under test (“DUT”) storing a given data signal according to a given clock signal is provided, wherein the testing apparatus includes a timing generating unit for generating sequentially a plurality of timing signals having different timings during the setup testing or the hold testing on the basis of a fist offset value given before starting the setup testing or the hold testing; a pattern generating unit for generating the clock signal and the data signal; a pattern formatting unit for shifting the phase of the data signal with respect to the clock signal sequentially according to the timing signals sequentially generated and providing the DUT with the clock signal and the phase-shifted data signal sequentially; and a determining module for acquiring a setup time or a hold time of the DUT on the basis of storage data which are the data signals stored by the DUT.

Abstract: The control device records, in advance, a current data table which specifies relationships between currents in respective phases in a three-phase motor and rotation angles of a rotor of the three-phase motor, obtains, from the current data table, a rotation angle of the rotor of the three-phase motor corresponding to a current in each phase in the three-phase motor detected by a current sensor before driving of the three-phase motor, and obtains an initial position of the rotor.

Abstract: There is provided a shift clock generator for phase-shifting a shift clock by inserting insertion pulses into the shift clock, wherein an insertion pulse generating section has a compensation memory for storing compensation data for calculating a number of insertion pulses to be inserted into the shift clock with respect to a phase difference preset value based on a phase shift amount, a number-of-pulses calculating section for integrating the compensation data stored in an address range of the compensation memory to calculate a number-of-insertion pulses data based on the phase difference preset value and a pulse generating section for generating the insertion pulses based on the number-of-insertion pulses data.

Abstract: Rear end face films of a first device portion and a second device portion have a first reflective film in which one or a plurality of sets of a first rear end face film with a refractive index of n1 and a second rear end face film with a refractive index of n2 (?n1) are layered on the rear end face; and a second reflective film in which one or a plurality of sets of a third rear end face film with a refractive index of n3 (?n1) and a fourth rear end face film with a refractive index of n4 (?n1) are layered on the first reflective film.

Abstract: A test apparatus includes a pattern memory for storing a test pattern to be inputted to a memory-under-test, an address generating section for sequentially outputting addresses of the memory-under-test into which the test pattern is to be written, a pointer section for sequentially pointing each address of the pattern memory to cause the pattern memory to output the test pattern in synchronism with the address of the memory-under-test outputted out of the address generating section, a bad block memory for storing an address of a bad block of the memory-under-test in advance and a pointer control section for causing the address generating section to output a next address of the memory-under-test while holding the address of the pattern memory outputted out of the pointer section when the address of the memory-under-test generated by the address generating section coincides with any one of addresses stored in the bad block memory.

Abstract: The present invention is intended to provide a liquid crystal optical element that is compatible with a plurality of types of recording media and that can compensate for aberration occurring during reading. The liquid crystal optical element in accordance with the present invention includes a first substrate, a second substrate, a liquid crystal provided between the first and second substrates, an electrode pattern formed on one of the first and second substrates and having an aperture control field and an aberration compensation field, and an opposite electrode, which is formed on the other one of the first and second electrodes, for applying a voltage between the electrode pattern and itself.

Abstract: There is provided a shift clock generator for phase-shifting a shift clock by inserting insertion pulses into the shift clock, wherein an insertion pulse generating section has a compensation memory for storing compensation data for calculating a number of insertion pulses to be inserted into the shift clock with respect to a phase difference preset value based on a phase shift amount, a number-of-pulses calculating section for integrating the compensation data stored in an address range of the compensation memory to calculate a number-of-insertion pulses data based on the phase difference preset value and a pulse generating section for generating the insertion pulses based on the number-of-insertion pulses data.

Abstract: The control device records, in advance, a current data table which specifies relationships between currents in respective phases in a three-phase motor and rotation angles of a rotor of the three-phase motor, obtains, from the current data table, a rotation angle of the rotor of the three-phase motor corresponding to a current in each phase in the three-phase motor detected by a current sensor before driving of the three-phase motor, and obtains an initial position of the rotor.

Abstract: There are provided a gas barrier film, which can undergo winding processing, is less likely to cause elongation or deflection upon exposure to heat or the like during processing or use, has a high level of dimensional stability, is less likely to be attacked by chemicals or the like during processing or use, can form a stable gas barrier layer, and has a high level of gas barrier properties against water vapor, oxygen and the like, and a display substrate and a display using said gas barrier film. The gas barrier film comprises: a base material film 11 having a deflection temperature under load of 150° C. or above; and at least a gas barrier layer 13A and a smoothing layer 15A in that order, or a smoothing layer 15A and a gas barrier layer 13A in that order provided on the base material film 11.

Abstract: The present invention provides a compact liquid crystal optical element for optical modulation and a compact optical device. A liquid crystal optical element for optical modulation is prepared by connecting two transparent substrates, each formed with a transparent electrode and an orientation film, with a sealing member, leaving a clearance between the two transparent substrates. On at least one surface of at least one of these transparent substrates, a diaphragm is formed using a shielding member. With this arrangement, it is possible to provide a more compact liquid crystal optical element than has been conventionally available. At the same time, it is possible to substantially reduce the occurrence of noise. Therefore, it is possible to provide a liquid crystal optical element and an optical device having excellent performance.

Abstract: A timing generator includes a reference clock generating unit for outputting a reference clock at a predetermined time interval, a first variable delay circuit unit for receiving the reference clock and outputting a first delay signal which results from delaying the reference clock, a second variable delay circuit unit for receiving the reference clock and outputting a second delay signal which results from delaying the reference clock, a delay control unit for controlling delay amounts of the first and second variable delay circuit units, and a timing generating unit for generating the timing signal based on the first and second delay signals, wherein the first and second delay control units increase or decrease the delay amounts of the first and second variable delay circuit units to be increased or decreased whenever the reference clock generating unit generates the reference clock.

Abstract: An inventive test apparatus has a timing comparator for obtaining an output value of an output signal outputted from a memory-under-test with timing of a strobe signal, a logical comparator for comparing the output value obtained by the timing comparator with an expected value and for outputting a comparison result and a phase adjustment control circuit for adjusting the timing of the strobe signal based on the comparison result outputted from the logical comparator. The inventive test apparatus further includes a first variable delay circuit for delaying and supplying the strobe signal to the timing comparator and the phase adjustment control circuit sets the delay effected by the first variable delay circuit based on the comparison result outputted from the logical comparator.

Abstract: A test apparatus for testing an electronic device includes a pattern generating unit for generating a test pattern to test the electronic device, a reference clock generating unit for generating a reference clock, a timing generator for generating a timing signal, an output signal sampling circuit for sampling the output signal outputted by the electronic device in response to the test pattern at the timing based on the timing signal generated by the timing generator, wherein the timing generator includes a variable delay circuit unit for receiving, delaying and outputting the reference clock, and a delay control unit for controlling the delay amount of the variable delay circuit unit, and the delay control unit controls the delay amount based on the basic timing data and the variable delay amount which is smaller than the basic timing data.

Abstract: A testing device that tests an electronic device includes a test pattern outputting unit operable to output a test pattern to the electronic device, a deciding unit operable to decide whether an output signal from the electronic device satisfies a predetermined condition, an instruction storing unit operable to store a plurality of instruction codes, a first instruction pipeline operable to generate a condition satisfaction instruction stream including a plurality of instructions that causes the test pattern outputting unit to output the test pattern to be supplied to the electronic device when the output signal satisfies the condition based on the plurality of instruction codes, a second instruction pipeline operable to generate a condition non-satisfaction instruction stream including a plurality of instructions that causes the test pattern outputting unit to output the test pattern to be supplied to the electronic device when the output signal does not satisfy the condition based on the plurality of instru