Patents by Inventor Shinya Sato

Shinya Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8338890
    Abstract: A semiconductor device includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one of the semiconductor substrates. In the device, the through electrode is electrically connected with the plurality of electrostatic discharge protection circuits.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: December 25, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Takayuki Saiki, Shinya Sato, Hiroyuki Takamiya
  • Publication number: 20120314375
    Abstract: A heat release device is for use with a multilayer board that has an inner layer serving as a power layer. The heat release device includes a heat release member thermally and electrically connected to the power layer, and a heat release board having a heat release layer and a shield layer electrically insulated from each other. The heat release layer is thermally and electrically connected to the heat release member. The shield layer serves to shield against electromagnetic noise radiated from the heat release layer. The shield layer is electrically insulated from the heat release member connected to the heat release layer. The heat release device also includes an electrically conductive member electrically connected to the shield layer and grounded, and an insulator through which the heat release layer is thermally connected to the electrically conductive member.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 13, 2012
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Shinya SATO, Hiroshi FUKASAKU
  • Publication number: 20120306263
    Abstract: A control device for an electrically powered vehicle, mounted to the electrically powered vehicle, includes: a current control element that takes off a charging current to be supplied to a low voltage battery in order to charge up the low voltage battery from an output current on the low voltage battery side of a voltage conversion device that performs voltage conversion between voltage of a high voltage battery and voltage of the low voltage battery; and an integrated control unit that determines a charging current value for the charging current based upon accumulated power information related to power accumulated in the low voltage battery and conversion efficiency of the voltage conversion by the voltage conversion device, and that controls the current control element so as to take off the charging current specified by the charging current value with the current control element.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 6, 2012
    Applicant: Hitachi Automotive Systems, Ltd.
    Inventors: Naoyuki TASHIRO, Shinya SATO, Hitoshi KOBAYASHI
  • Patent number: 8247841
    Abstract: A semiconductor device includes: a plurality of semiconductor substrates that are layered; a through electrode penetrating through a predetermined semiconductor substrate of the semiconductor substrates and electrically connected with an external terminal of the semiconductor device; a circuit element provided on the predetermined semiconductor substrate; and an electrostatic discharge protection circuit also provided on the predetermined semiconductor substrate. In the device, wiring resistance between the electrostatic discharge protection circuit and the through electrode is smaller than wiring resistance between the circuit element and the through electrode.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 21, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Takayuki Saiki, Shinya Sato, Hiroyuki Takamiya
  • Publication number: 20120123624
    Abstract: A running control device for an electric vehicle includes: a first calculation unit that calculates a predetermined reference torque required for braking/driving the motor that provides a beneficial effect with regard to power consumption of the electric vehicle; a second calculation unit that calculates interval allocation between a first interval in which the electric vehicle is propelled by braking/driving the motor at the predetermined reference torque and a second interval in which the electric vehicle is coasted without the motor being braked or driven; a third calculation unit that calculates a control requested torque for braking/driving the motor intermittently, so as alternatingly to repeat running of the electric vehicle in the first intervals and coasting of the electric vehicle in the second intervals; and a running control unit that performs running control of the electric vehicle by braking/driving the motor intermittently according to the control requested torque.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 17, 2012
    Applicant: Hitachi, Ltd.
    Inventors: Shinya SATO, Naoyuki Tashiro, Kentaro Maki, Atsushi Yokoyama
  • Patent number: 8121168
    Abstract: A multibeam laser diode capable of improving heat release characteristics in the case of junction-down assembly is provided. Contact electrodes are provided respectively for protruding streaks of a laser diode device, and pad electrodes are provided to avoid the protruding streaks and the contact electrodes. The contact electrodes and the pad electrodes are connected by wiring electrodes, and the contact electrodes are covered with a first insulating film. Thereby, electric connection is enabled without straightly jointing the contact electrodes to a solder layer. A heat conduction layer configured of a metal is provided on the first insulating film, the heat conduction layer is jointed to the solder layer, and thereby the heat release characteristics are able to be improved even in the case of junction-down assembly.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: February 21, 2012
    Assignee: Sony Corporation
    Inventor: Shinya Sato
  • Patent number: 8105542
    Abstract: A selective reduction catalyst includes a catalyst support in which a plurality of through holes partitioned by porous walls are formed in parallel with each other and an active component having a catalytic action and carried by the walls. Inlet portions and outlet portions, adjacent to each other, of the through holes are alternately sealed, and the wall carrying the active component is formed so that a particle-state solid matter ammonium nitrate cannot pass through it. The exhaust gas purifier includes the selective reduction catalyst, a liquid injection nozzle which is provided on the upstream side and can inject urea liquid toward the catalyst, a diesel particulate filter provided at an exhaust pipe on the upstream side, and filter temperature raising means capable of raising the temperature of the diesel particulate filter to a predetermined value or above.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: January 31, 2012
    Assignee: Hino Motors, Ltd.
    Inventors: Shinya Sato, Mitsuru Hosoya
  • Patent number: 8105545
    Abstract: A selective reduction catalyst includes a catalyst support in which a plurality of through holes partitioned by porous walls are formed and a first active component carried by the walls which dissolves nitrogen oxide contained in the exhaust gas by the reaction with ammonia. Inlet portions and outlet portions, adjacent to each other, of the plurality of through holes are alternately sealed, and the wall carrying the first active component has ventilation and a second active component having a catalytic action so as to oxidize ammonia having passed the wall is carried on the inner surface of the though hole. An exhaust gas purifier is provided with the selective reduction catalyst, a liquid injection nozzle which is provided on the upstream side and can inject urea liquid, and an oxidation catalyst provided at the exhaust pipe on the upstream side.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: January 31, 2012
    Assignee: Hino Motors, Ltd.
    Inventor: Shinya Sato
  • Publication number: 20120022735
    Abstract: A drive control device for an electric vehicle that is driven by a motor-generator, includes: a detection unit that detects a fact that an accelerator pedal depression amount and a brake pedal depression amount of the electric vehicle are both zero; and a control unit that sets a regenerative braking torque command value for the motor-generator to zero, while the detection unit is detecting the fact.
    Type: Application
    Filed: July 21, 2011
    Publication date: January 26, 2012
    Inventors: Naoyuki Tashiro, Ryo Inaba, Shinya Sato
  • Patent number: 8074130
    Abstract: A test apparatus includes a test section that executes testing of each cell of the memory under test, a fail information storage section that stores fail information in a fail memory; a counting section that counts the number of defective cells in each block, a reading request receiving section that receives a request to read the fail information of each cell, a comparing section that compares the number of defective cells in a block to a predetermined reference number, a converting section that, in a case where the number of defective cells exceeds the predetermined reference value, converts a plurality of consecutive pieces of fail information in a response data string into a value indicating defectiveness, and a compressing section that compresses the response data string and returns a compressed response data string.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: December 6, 2011
    Assignee: Advantest Corporation
    Inventor: Shinya Sato
  • Patent number: 8057927
    Abstract: A magnetic recording medium includes a nonmagnetic granular layer that has a granular structure in which a plurality of nonmagnetic grains made of a nonmagnetic material are separated from one another by a Cr oxide. The magnetic recording medium further includes a magnetic granular layer that is formed on the nonmagnetic granular layer and has a granular structure in which a plurality of magnetic grains made of a magnetic material are separated from one another by a nonmagnetic material.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: November 15, 2011
    Assignee: Showa Denko K.K.
    Inventors: Satoshi Igarashi, Tohru Horie, Ryo Kurita, Isatake Kaitsu, Akira Kikuchi, Shinya Sato
  • Publication number: 20110191739
    Abstract: A circuit design method for interconnecting a plurality of modules includes: a step of acquiring port information including input ports and output ports of the plurality of modules; a step of acquiring instance information indicating that, among the plurality of modules, there is a module including a plurality of instances having the same function; and a step of associating the input ports and the output ports based on the port information and the instance information to interconnect the plurality of modules.
    Type: Application
    Filed: September 25, 2009
    Publication date: August 4, 2011
    Applicant: ADVANTEST CORPORATION
    Inventors: Takashi Hasegawa, Shinya Sato
  • Patent number: 7984345
    Abstract: A test apparatus compares bits included in a data sequence read from a DUT with expectation values. Comparison results are stored in a first failure memory (FM) as bit information indicating whether storage cells of the DUT are non-defective. The storage device counts the number of bits not matching the expectation values for each page, and judges for each grade/page of the DUT whether the number of bits not matching the expectation values meets the condition of that grade. Judgment results are stored in a second FM as page information indicating whether each page is non-defective for each grade. If page information of a page including a bit corresponding to a storage cell indicating that this page meets the condition of any grade is stored in the second FM, the apparatus outputs the bit information in the first FM, by changing it to a value indicating that storage cell is as non-defective.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: July 19, 2011
    Assignee: Advantest Corporation
    Inventors: Taiki Ozawa, Shinya Sato
  • Publication number: 20110169081
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first semiconductor layer is formed with a trench. The second semiconductor layer is buried in the trench, and includes a hollow portion. A length of the hollow portion along depth direction of the trench is 5 ?m or less or 15 ?m or more.
    Type: Application
    Filed: January 7, 2011
    Publication date: July 14, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hironori Ishikawa, Shinya Sato, Hiroyuki Sugaya, Tomoyuki Sakuma
  • Patent number: 7974051
    Abstract: An interface circuit is provided between a first circuit block and a second circuit block that operates using a power supply system differing from that of the first circuit block. An electrostatic discharge protection circuit that include a PN diode and a diffused resistor is formed in order to prevent electrostatic discharge destruction of a gate insulating film of a transistor that forms the interface circuit. The electrostatic discharge protection circuit may be formed using the remaining basic cells of a gate array that forms the second circuit block. An electrostatic discharge protection circuit formed of a bidirectional diode may be connected between a first low-potential power supply and a second low-potential power supply.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: July 5, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Shinya Sato, Takayuki Saiki, Hiroyuki Takamiya
  • Patent number: 7945826
    Abstract: Provided is a test apparatus having a bad block memory for storing a plurality of pieces of fail information in association with blocks of a memory under test, each piece of fail information indicating whether there is a defect in the associated block. The test apparatus writes a test data sequence to a page under test of the memory under test, reads the test data sequence written to the page under test, and compares the read data sequence to the written data sequence. The test apparatus includes an allocation register that stores allocation information for setting which of the plurality of fail conditions for judging whether there is a defect in the page under test are allocated to the plurality of pieces of fail information.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: May 17, 2011
    Assignee: Advantest Corporation
    Inventors: Satoshi Kameda, Masaru Doi, Shinya Sato
  • Patent number: 7930614
    Abstract: A test apparatus is provided for testing memory under test which stores a data string including an error correction code in the form of additional data. The test apparatus comprises: a logic comparator which compares each of the data sets included in a data string read out from the memory under test with a corresponding anticipated value created beforehand; a data error count unit which counts the number of data sets that do not match the respective anticipated values; and a defect detection unit which provides a function whereby, in a case that the count value counted by the error count unit exceeds a predetermined upper limit number which is equal to or greater than 1, determination is made that the memory under test is defective.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: April 19, 2011
    Assignee: Advantest Corporation
    Inventor: Shinya Sato
  • Patent number: 7904765
    Abstract: Provided is a test apparatus including: test signal supply sections supplying a test signal writing test data to the connected memory under test, to a terminal of the memory; terminal correspondence determination sections outputting a terminal unit determination result indicating whether test data from the connected terminal matches an expected value; a determination result selection section selecting, for each memory, terminal unit determination results from the terminal correspondence determination sections; a memory correspondence determination section determining whether writing succeeded to each memory, based on the selection result by the determination result selection section; an identifying section identifying a test signal supply section connected to the memory to which writing succeeded and a test signal supply section connected to the memory to which writing failed; and a mask treatment section instructing each test signal supply section whether to perform re-testing, according to whether writing s
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: March 8, 2011
    Assignee: Advantest Corporation
    Inventors: Masahiko Hata, Shinya Sato
  • Patent number: 7839458
    Abstract: A first electrode of a liquid crystal cell (21) is composed of a plurality of concentric electrodes (31 to 34) of a concentrically circular shape, the plurality of concentric electrodes are divided into a first group of concentric electrodes (44) near the center and a second group of concentric electrodes (45) near the periphery, and a concentric electrode between the two groups is an independent single electrode (36). A first correction unit that corrects spherical aberration of a high density DVD is composed of the two groups and a second correction unit that corrects aberration of a conventional DVD is composed of the first group of concentric electrodes (44). In the case of correcting the aberration of the conventional DVD, the independent concentric electrode (36) is supplied with a voltage between the voltages respectively supplied to adjacent concentric electrodes (35), (37).
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: November 23, 2010
    Assignee: Citizen Holdings Co., Ltd.
    Inventors: Seiichi Osawa, Shinya Sato, Masayuki Iwasaki, Takeshi Toyoda
  • Publication number: 20100254862
    Abstract: A first porous catalytic layer is provided in an exhaust passage, and a second porous catalytic layer is stacked on the exhaust-gas downstream-side surface of the first layer. The first layer includes an iron-zeolite catalyst to decrease 60% or more of NOx in the exhaust gas within an exhaust gas temperature range of 150-400° C. The second layer includes one or more of a single catalyst, a mixed catalyst, and a complex oxide catalyst selected from iron-alumina, iron-zirconia, iron-ceria, and iron-titania, to decrease 60% or more of NOx in the exhaust gas within an exhaust gas temperature range of 400-700° C. The first and second layers cooperatively exhibit catalytic activity to decrease 70% or more of NOx in the exhaust gas within an exhaust gas temperature range of 150 to 700° C.
    Type: Application
    Filed: October 27, 2008
    Publication date: October 7, 2010
    Inventors: Shinya Sato, Yoshihiro Kawada, Mitsuru Hosoya