Abstract: In a successive approximation AD converter, a noise generator outputs the output of a ?? modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.

Abstract: A capacitor array includes a plurality of comb capacitors sharing a common comb electrode. At least one of the comb capacitors has a comb electrode as a single base part. Each of the other ones of the comb capacitors has an electrode formed by coupling a plurality of base parts. In the other ones of the comb capacitors, a space between a wire coupling the base parts and an end of each of comb teeth of the common electrode, which is interposed between the base parts, is larger than a space between a base of each of the base parts of the plurality of comb capacitors and an end of each of the comb teeth of the common electrode, which is interposed between comb teeth of the base part.

Abstract: A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Abstract: A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC.

Abstract: A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time ?? A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time ?? A/D converters to feed back the digital signal to the digital filter.

Abstract: In a successive approximation AD converter, a noise generator outputs the output of a ?? modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.

Abstract: A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC.

Abstract: A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Abstract: A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time ?? A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time ?? A/D converters to feed back the digital signal to the digital filter.

Abstract: An oscillator circuit complementarily increases or reduces, in response to a transition of a signal level of a reference clock, a signal level of a first oscillation signal and a signal level of a second oscillation signal. An oscillation control circuit compares the first and second oscillation signals to a comparison voltage, and transitions the signal level of the reference clock in accordance with a result of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. A reference voltage control circuit increases or reduces the reference voltage according to a frequency difference between a basis clock and the reference clock.

Abstract: A sampling clock generator generates a sampling clock based on a reference clock and an internal clock. An internal clock generator causes, during a period in which the sampling clock is at a second voltage level, the internal clock to transition from a first voltage level to a second voltage level when a first comparison signal and a second comparison signal transition to voltage levels different from each other, and the internal clock to transition from the second voltage level to the first voltage level after a variable delay time has elapsed when the first and second comparison signals transition to a same voltage level. A delay controller controls the variable delay time in the internal clock generator so that the ratio of a period in which the sampling clock is at a first voltage level to a period of the reference clock approaches a predetermined ratio.

Abstract: A controller controls first and second supply switches so that, during a sampling period, a ground voltage is supplied to n first up-capacitors and n second up-capacitors while a power supply voltage is supplied to n first down-capacitors and n second down-capacitors. The controller also controls the first and second supply switches based on the result of comparison by a comparator during each of n bit determination periods so that a first analog voltage at a first sampling node and a second analog voltage at a second sampling node gradually approach each other.

Abstract: An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.

Abstract: In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.

Abstract: The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

Abstract: A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.

Abstract: An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.

Abstract: A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

Abstract: In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.

Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.