Abstract: The switching regulator of a synchronous rectifying mode comprises the first and second switches SW1, SW2 arranged in series between the power source Vdd and the ground Vss, the switch control unit 1 which controls the on-off operation of the switches SW1, SW2, and the smoothing circuit 4 which smoothes the output node potential Vnd. When the signal Sc1 indicates that the output node potential Vnd goes below the first reference potential Vr1 which is the reference to detect the occurrence of the inrush current while the first switch SW1 is in the ON state, the control circuit 10 turns off the first switch SW1. Thus, the detection of the inrush current is conducted by making use of a voltage drop due to the on resistance of the first switch SW1, so that it is unnecessary to provide a resistance element for detecting the inrush current.

Abstract: A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source.

Abstract: A neural network circuit for performing a processing of recognizing voices, images and the like comprises a weight memory for holding a lot of weight values (initial weight values) which correspond to a plurality of input terminals of each of a plurality of neurons forming a neural network and have been initially learned, and a difference value memory for storing difference values between the weight values of the weight memory and additionally learned weight values. The weight memory is formed by a ROM. The difference value memory is formed by a SRAM, for example. During operation of recognizing input data, the initial weight values of the weight memory and the difference values of the difference value memory are added together. The added weight values are used to calculate an output value of each neuron of an output layer. Accordingly, the initial weight values can be additionally learned at a high speed by existence of the difference value memory having a small capacity.

Abstract: A reference voltage output terminal of first and second reference voltage generating circuits is connected to a first current input terminal of a current mirror circuit of an operational amplifier by a diode element. At the time of start-up, a reference voltage generated on the reference voltage output terminal is 0 V. Consequently, a current flows to the diode element and an offset voltage Voff is generated on the operational amplifier so that a malfunction point is caused to disappear. Accordingly, in the case where a normal operation point on which a reference voltage having an expected value is generated and a malfunction point on which an operation is stabilized with a reference voltage having a value less than the expected value are present, the generated reference voltage is raised at the time of start-up, passes through the malfunction point to reach an expected voltage value on the normal operation point and becomes stabilized.

Abstract: In an interpolative modulator, a signal which varies by only .+-.1 with one clock from a 1-bit quantizer is used as a shift-direction control signal. The shift-direction control signal is given to a bidirectional shift register. The bidirectional shift register shifts data based on the value of the shift-direction control signal that has been received. The output from the bidirectional shift register is given as a control signal to a resistive-ladder-type D/A converter. The resistive-ladder-type D/A converter outputs an analog potential corresponding to a switch selected by the above control signal. Therefore, if a delay difference occurs between any two bits, two adjacent switches are simply selected simultaneously, so that the output from the resistive-ladder-type D/A converter varies continuously. Consequently, there can be provided an oversampling D/A converter of resistive-ladder type with high accuracy and an increased yield, which is free from glitch (transiently generated noise).

Abstract: In a multilayered neural network for recognizing and processing characteristic data of images and the like by carrying out network arithmetical operations, characteristic data memories store the characteristic data of the layers. Coefficient memories store respective coupling coefficients of the layers other than the last layer. A weight memory stores weights of neurons of the last layer. Address converters carry out arithmetical operations to find out addresses of nets of the network whose coupling coefficients are significant. A table memory outputs a total coupling coefficient obtained by inter-multiplying the significant coupling coefficients read out from the coefficient memories of the layers. A cumulative operation unit performs cumulative additions of the product of the total coupling coefficient times the weight of the weight memory. Arithmetical operations are carried out only on particular nets with a significant coupling coefficient value. The speed of operation and recognition can be improved.

Abstract: In an information processing apparatus for implementing a neural network, if an input vector is inputted to a calculating unit, a neuron which responds to the input vector is retrieved in accordance with network interconnection information stored in a first storage unit and the neuron number indicating the retrieved neuron is written in a first register. The calculating unit reads out the internal information of the neuron stored in a second storage unit by using the neuron number, writes it in a second register, and calculates the sum of products of the outputs of the neurons and the connection loads of synapses connected to the neurons. By repeating the sequence of operations by the number of times corresponding to the total number of input vectors, a recognition process is executed. The neural network can easily be expanded by rewriting the contents of the first and second storage units.

Abstract: The present invention provides a first-order delta-sigma AD converter adapted to conduct noise shaping and having a quantizer arranged such that, when the amplitude of an input signal entered into the quantizer is small, the amplitude of a difference signal between the input signal entered into the quantizer and an output signal therefrom, is small. It is therefore possible to achieve an efficient AD- or DA-converter reduced in power consumption, which satisfies the transmission characteristics of the specifications of CCITT G.714 based on a method of PCM-encoding an audio frequency band signal stipulated in the specifications of CCITT G.711.

Abstract: In a multi-layered neural network circuit provided with an input layer having input vectors, an intermediate layer having networks in tree-like structure whose outputs are necessarily determined by the values of the input vectors and whose number corresponds to the number of the input vectors of the input layer, and an output layer having plural output units for integrating all outputs of the intermediate layer, provided are learning-time memories for memorizing the numbers of times at learning in paths between the intermediate layer and the respective output units, threshold processing circuits for threshold-processing the outputs of the leaning-time memories, and connection control circuits to be controlled by the outputs of the threshold processing circuits for controlling connection of paths between the intermediate layer and the output units. The outputs of the intermediate layer connected by the connection control circuits are summed in each output unit.

Abstract: In a direct type of finite impulse response (FIR) digital filter, direct type digital filters consisting a plurality of taps are used as a construction element of a digital filter. A pipeline structure is constructed between cascaded construction elements, and the sum and carry signals of the multi-input addition in the midst of the addition operation are transferred between cascaded construction elements. The number of gates, dissipation power, chip area and the like can be decreased as compared with a prior art inverted type digital filter. Further, a digital signal processing system such as a waveform equalizing system can be constructed using a direct type digital filter as mentioned above, and such a system includes a selector for selecting the output of the digital filter and an output in the midst of the delays in the digital filter.

Abstract: A digital signal processing system includes a plurality of multiplier/accumulators for executing a pipeline processing operation. Each of the plurality of multiplier/accumulators includes a multiplication part and an addition part. The multiplication parts includes N pipeline registers for storing N intermediate outputs of a multiplier. The addition part includes a Wallace tree transformation unit for transforming a sum of N+1 inputs into two transformation outputs, and an adder for adding the two transformation outputs. The N+1 inputs includes the N intermediate outputs from the multiplication part and the one addition output from the adder.

Abstract: A local image processor is configured as a plurality of image processor elements each having a local image memory, and a single shift register circuit for supplying to the local image memories successive local images formed of an array of pixels of a source image. Each processor element includes a register holding a count value indicating the position within the source image of data that are currently being processed by that element, and the processor elements also include mutually interconnected registers whereby intermediate computation results obtained by one processor element can be utilized by another element during parallel processing operation.