Abstract: A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.

Abstract: A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

Abstract: A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

Abstract: Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.

Abstract: A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.

Abstract: Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0 to LS7) are equal to each other.

Abstract: A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

Abstract: In a device for generating a clock signal having a desired phase from input multi-phase clock signals, an intermediate clock generator generates, by using one of the input multi-phase clock signals as a reference clock signal, multi-phase intermediate clock signals in which one cycle is equal to a plurality of cycles of the reference clock signal. A first phase selector selects one of the multi-phase intermediate clock signals. A second phase selector selects one of the multi-phase clock signals. A latch circuit latches the intermediate clock signal selected by the first phase selector with the clock signal selected by the second phase selector.

Abstract: A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

Abstract: A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.

Abstract: A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

Abstract: A reference voltage generation circuit of the present invention includes: a band gap reference-type current generation circuit for controlling each of currents flowing through a first current path and a second current path, which are extending from a first node to a second node, to be a predetermined reference current, by utilizing a voltage difference occurring between a pair of transistors or diodes; and a resistive load circuit provided between the second node and a third node.

Abstract: An A/D converter includes: a plurality of A/D conversion circuits (10 a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.

Abstract: Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.

Abstract: An A/D converter includes: a plurality of A/D conversion circuits (10a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.

Abstract: Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.

Abstract: In a device for generating a clock signal having a desired phase from input multi-phase clock signals, an intermediate clock generator generates, by using one of the input multi-phase clock signals as a reference clock signal, multi-phase intermediate clock signals in which one cycle is equal to a plurality of cycles of the reference clock signal. A first phase selector selects one of the multi-phase intermediate clock signals. A second phase selector selects one of the multi-phase clock signals. A latch circuit latches the intermediate clock signal selected by the first phase selector with the clock signal selected by the second phase selector.

Abstract: Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0 to LS7) are equal to each other.

Abstract: A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.

Abstract: In a semiconductor integrated circuit of the present invention, the main circuit 2 includes MOS transistors in which the source and the substrate are separated from each other. The substrate potential control circuit 1 controls the substrate potential of the MOS transistors of the main circuit 2 so that the actual saturation current value of the MOS transistors of the main circuit 2 is equal to the target saturation current value Ids under the operating power supply voltage Vdd of the main circuit 2. Therefore, it is possible to suppress variations in the operation speed even if the operating power supply voltage of the semiconductor integrated circuit is reduced.