Abstract: The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

Abstract: A two-level supply voltage detection circuit includes two power supply detection circuits. One of the power supply detection circuits is provided on the high potential side, and the other is provided on the lower potential side. Each power supply detection circuit outputs a detection signal which is active when the supply voltage is equal to or higher than a reference value. The two-level supply voltage detection circuit outputs an OR logic value of the detection outputs of the power supply detection circuits. Furthermore, the power supply detection circuit on the low voltage side includes a detection operation control circuit. Only when a detection signal output from the power supply detection circuit on the high voltage side is active, the detection operation control circuit turns off the power supply detection circuit on the low voltage side in response to the active detection signal.

Abstract: A large chip includes a first set of branch wires that branch off from a first trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the first set includes a connection control element and a resistor. A small chip includes a second set of branch wires that branch off from a second trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the second set includes a connection control element and a resistor. Whether connection is properly made or not between the bond pads is determined by measuring a current value when voltage is applied to first and second test pads.

Abstract: A two-level supply voltage detection circuit includes two power supply detection circuits. One of the power supply detection circuits is provided on the high potential side, and the other is provided on the lower potential side. Each power supply detection circuit outputs a detection signal which is active when the supply voltage is equal to or higher than a reference value. The two-level supply voltage detection circuit outputs an OR logic value of the detection outputs of the power supply detection circuits. Furthermore, the power supply detection circuit on the low voltage side includes a detection operation control circuit. Only when a detection signal output from the power supply detection circuit on the high voltage side is active, the detection operation control circuit turns off the power supply detection circuit on the low voltage side in response to the active detection signal.

Abstract: In a cell library database, timing verification is conducted on an LSI which exists in a variable power supply system capable of changing the source voltage arbitrarily and which includes logic delay information associated with a plurality of source voltages. The database is configured, for example, so that the voltage information V of the source is represented in multiple bits V [1:0] and delay times Alh (Vlh) to Bhl (Vhh) between the time input signals A and B are each changed and the time the output signal Y changes are described for respective pieces of source voltage information LH (1.2 V), HL (1.5 V) and HH (1.8 V). This allows timing verification in the variable source system which operates with the source voltage changed dynamically.

Abstract: A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground.

Abstract: A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit. As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics.

Abstract: A multi-chip module is implemented by connecting a plurality of connection pads provided on, for example, two semiconductor chips via a plurality of conductive connecting members. To carry out a test for determining the quality of the connection between the two semiconductor chips, the multi-chip module is further provided with a plurality of switch elements so that the plurality of connecting members can be electrically conducted in a serial manner via the connection pads of the semiconductor chips. During the connection test, all the switch elements are turned on, and the impedance between both ends of the line including the plurality of connecting members conducted in a serial manner is measured using two probing pads.

Abstract: During an intermittent operation mode, a switch is normally opened and a capacitor with a large capacitance is isolated from a circuit. Under this condition, a power source voltage is intermittently supplied to a driven device. Since a charge/discharge current of the capacitor during the intermittent operation mode is limited to the charge/discharge current of the capacitor with a small capacitance, the power consumption can be lowered. In addition, since no switch exists in the current path from a power source voltage conversion circuit to the driven device, there is no drop, due to a switch, in the voltage supplied from the power source voltage conversion circuit to the driven device. On the other hand, during a continuous operation mode in which power source voltage is continuously provided to the driven device, the switch is normally closed and a capacitor with a large capacitance is connected to the power source system. Then the noise level in the supplied power is lowered.

Abstract: A power supply device is provided in which, in order to increase a rise speed of an output voltage and to suppress a voltage drop when switching between power supply devices, during a second operation mode in which power supply is stopped, an output switch is turned off and a reference voltage generating circuit applies a reference voltage Vref2, which equals a gate voltage in a steady state during power supply (first operation mode), to the gate of an output transistor. Thus, when entering the first operation mode, the feedback operation of a differential operational amplifier quickly reaches a steady state. In addition, during the second operation mode, a switch that supplies power to the reference voltage generating circuit and the differential operational amplifier is open, reducing the power consumption of the power supply device itself.

Abstract: A large chip includes a first set of branch wires that branch off from a first trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the first set includes a connection control element and a resistor. A small chip includes a second set of branch wires that branch off from a second trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the second set includes a connection control element and a resistor. Whether connection is properly made or not between the bond pads is determined by measuring a current value when voltage is applied to first and second test pads.

Abstract: A cell library database includes function information of standard cells which are basic circuits forming a logical device, each of the standard cell comprising at least one of power supply terminal as logical terminals, the function information of the standard cell containing logical information or delay information of the power supply terminal relative to an output terminal, or function information of macro cells which are functional circuits forming a logical device, each of the macro cell comprising at least one of power supply terminals as logical terminals, the function information of the macro cell containing logical information or delay information of said power supply terminals relative to an output terminal. A design aiding system uses the cell library database to execute logical simulation, etc.

Abstract: A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit. As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics.

Abstract: Each bare-chip IP includes pad electrodes that are of the same size and shape, made of the same material, and arranged in an array at the same pitch over almost the entire surface thereof. A silicon wiring substrate includes pad electrodes that are arranged in an array over almost the entire surface thereof at the same pitch as that between the pad electrodes of the bare-chip IPs. The bare-chip IPs are mounted on the silicon wiring substrate, thereby making a multichip module.

Abstract: In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated nadescending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102.

Abstract: A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground.

Abstract: A frequency-voltage conversion circuit 21 receives a clock CLK as an input and provides a voltage IVdd in accordance with the frequency of the clock as an output. The input and output characteristic of the frequency-voltage conversion circuit 21 is adjusted to substantially match a given input and output characteristic.

Abstract: Each bare-chip IP includes pad electrodes that are of the same size and shape, made of the same material, and arranged in an array at the same pitch over almost the entire surface thereof. A silicon wiring substrate includes pad electrodes that are arranged in an array over almost the entire surface thereof at the same pitch as that between the pad electrodes of the bare-chip IPs. The bare-chip IPs are mounted on the silicon wiring substrate, thereby making a multichip module.

Abstract: In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated in a descending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102.

Abstract: During an intermittent operation mode, a switch is normally opened and a capacitor with a large capacitance is isolated from a circuit. Under this condition, a power source voltage is intermittently supplied to a driven device. Since a charge/discharge current of the capacitor during the intermittent operation mode is limited to the charge/discharge current of the capacitor with a small capacitance, the power consumption can be lowered. In addition, since no switch exists in the current path from a power source voltage conversion circuit to the driven device, there is no drop, due to a switch, in the voltage supplied from the power source voltage conversion circuit to the driven device. On the other hand, during a continuous operation mode in which power source voltage is continuously provided to the driven device, the switch is normally closed and a capacitor with a large capacitance is connected to the power source system. Then the noise level in the supplied power is lowered.