Patents by Inventor Shizunori Matsumoto

Shizunori Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11114498
    Abstract: An image signal output unit is controlled in accordance with a first control signal indicating either voltage state of an on voltage for causing a conductive state and an off voltage having a polarity different from that of the on voltage, and outputs an analog image signal corresponding to the electric charge held by an electric charge holding unit in the conductive state. A reset unit is controlled in accordance with a second control signal indicating either voltage state of the on voltage and the off voltage, resets the electric charge holding unit in the conductive state, transmits a fluctuation in the off voltage to the electric charge holding unit, and fluctuates the analog image signal. A reference signal generation unit generates a reference signal being a signal serving as a reference used when conversion from an analog image signal output from the image signal output unit into a digital image signal is performed.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 7, 2021
    Assignee: SONY CORPORATION
    Inventors: Tatsuki Nishino, Yosuke Ueno, Yusuke Moriyama, Shizunori Matsumoto
  • Patent number: 11095278
    Abstract: A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a third transistor that connects the first transistor to a power source voltage; a fourth transistor that connects the second transistor to the power source voltage; a fifth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the third transistor; and a sixth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the fourth transistor.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: August 17, 2021
    Assignee: Sony Corporation
    Inventors: Hideki Tanaka, Shizunori Matsumoto, Haruhisa Naganokawa, Yuuichi Kaji
  • Publication number: 20210075990
    Abstract: The present technology is provided to accurately correct uneven luminance while suppressing an increase in the size of the solid-state imaging element. A pixel array unit includes a plurality of lines each including a predetermined number of pixels each being arrayed in a predetermined direction. An analog-to-digital conversion unit includes more than the predetermined number of analog-to-digital converters that convert analog signals into digital signals. A scanning circuit controls to sequentially select the plurality of lines and output more than the predetermined number of analog signals to the analog-to-digital conversion unit every time the line is selected. A correction unit performs black level correction processing on the digital signal.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Inventors: ATSUMI NIWA, SHIZUNORI MATSUMOTO, EIJI HIRATA
  • Patent number: 10880509
    Abstract: The present technology is provided to accurately correct uneven luminance while suppressing an increase in the size of the solid-state imaging element. A pixel array unit includes a plurality of lines each including a predetermined number of pixels each being arrayed in a predetermined direction. An analog-to-digital conversion unit includes more than the predetermined number of analog-to-digital converters that convert analog signals into digital signals. A scanning circuit controls to sequentially select the plurality of lines and output more than the predetermined number of analog signals to the analog-to-digital conversion unit every time the line is selected. A correction unit performs black level correction processing on the digital signal.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 29, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Atsumi Niwa, Shizunori Matsumoto, Eiji Hirata
  • Patent number: 10840283
    Abstract: An imaging element comprises a photoelectric conversion unit formed in a pixel region and configured to convert light into electrical charge. Further, the imaging element includes a transistor formed in the pixel region and configured to transfer electric charge from the photoelectric conversion unit. The photoelectric conversion unit of the imaging element may be connected to a well of the pixel region, where the well of the pixel region has a negative potential.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: November 17, 2020
    Assignee: Sony Corporation
    Inventors: Yosuke Ueno, Yusuke Ikeda, Shizunori Matsumoto, Tsutomu Haruta, Rei Yoshikawa
  • Publication number: 20200314375
    Abstract: To control an excess bias to an appropriate value in a light detection device. A solid-state image sensor includes a photodiode, a resistor, and a control circuit. In this solid-state image sensor, the photodiode photoelectrically converts incident light and outputs a photocurrent. Furthermore, in the solid-state image sensor, the resistor is connected to a cathode of the photodiode. Furthermore, in the solid-state image sensor, the control circuit supplies a lower potential to an anode of the photodiode as a potential of the cathode of when the photocurrent flows through the resistor is higher.
    Type: Application
    Filed: August 24, 2018
    Publication date: October 1, 2020
    Inventors: Tatsuki Nishino, Hiroki Hiyama, Shizunori Matsumoto, Takahiro Miura, Akihiko Miyanohara, Tomohiro Matsumoto
  • Patent number: 10784306
    Abstract: A solid-state imaging device includes a layout in which one sharing unit includes an array of photodiodes of 2 pixels by 4√ón pixels (where, n is a positive integer), respectively, in horizontal and vertical directions.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: September 22, 2020
    Assignee: Sony Corporation
    Inventors: Kazuichiro Itonaga, Shizunori Matsumoto
  • Publication number: 20200295079
    Abstract: An image signal output unit is controlled in accordance with a first control signal indicating either voltage state of an on voltage for causing a conductive state and an off voltage having a polarity different from that of the on voltage, and outputs an analog image signal corresponding to the electric charge held by an electric charge holding unit in the conductive state. A reset unit is controlled in accordance with a second control signal indicating either voltage state of the on voltage and the off voltage, resets the electric charge holding unit in the conductive state, transmits a fluctuation in the off voltage to the electric charge holding unit, and fluctuates the analog image signal. A reference signal generation unit generates a reference signal being a signal serving as a reference used when conversion from an analog image signal output from the image signal output unit into a digital image signal is performed.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 17, 2020
    Inventors: TATSUKI NISHINO, YOSUKE UENO, YUSUKE MORIYAMA, SHIZUNORI MATSUMOTO
  • Patent number: 10707264
    Abstract: To prevent a decline in image quality by reducing a fluctuation in an image signal that is based on a fluctuation in a voltage of a negative voltage power source. An image signal output unit is controlled in accordance with a first control signal indicating either voltage state of an on voltage for causing a conductive state and an off voltage having a polarity different from that of the on voltage, and outputs an analog image signal corresponding to the electric charge held by an electric charge holding unit in the conductive state. A reset unit is controlled in accordance with a second control signal indicating either voltage state of the on voltage and the off voltage, resets the electric charge holding unit in the conductive state, transmits a fluctuation in the off voltage to the electric charge holding unit, and fluctuates the analog image signal.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: July 7, 2020
    Assignee: SONY CORPORATION
    Inventors: Tatsuki Nishino, Yosuke Ueno, Yusuke Moriyama, Shizunori Matsumoto
  • Patent number: 10694124
    Abstract: The present technique relates to an image pickup element and an electronic apparatus which enable a higher-quality image to be obtained. An image pickup element includes an input sense portion configured to produce a noise correction signal portion includes a first transistor and a second transistor configuring a current mirror circuit, a switch provided between a gate of the first transistor and a gate of the second transistor, and a capacitive element one electrode of which is connected between the switch and the gate of the second transistor on an output side of the current mirror circuit, and the other electrode of which is connected to the predetermined power source.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: June 23, 2020
    Assignee: Sony Corporation
    Inventors: Tatsuki Nishino, Yosuke Ueno, Yusuke Moriyama, Shizunori Matsumoto
  • Patent number: 10630930
    Abstract: The present disclosure relates to a solid-state image sensing apparatus, a control method, and an electronic device capable of reducing a settling time of a vertical signal line at the time of a read operation of pixels. A column processing unit A/D converts pixel signals of a plurality of pixels. A vertical signal line feeds the pixel signals output from the pixels to the A/D converter. A pull-up circuit increases a potential of the vertical signal line at the time of starting a read operation of the pixels. For example, the present disclosure can be applied to a CMOS (Complementary Metal-Oxide Semiconductor) image sensor that performs an interleaving operation or the like.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: April 21, 2020
    Assignee: Sony Corporation
    Inventors: Shizunori Matsumoto, Pawankumar Pradeepkumar Moyade
  • Publication number: 20200098805
    Abstract: An imaging element comprises a photoelectric conversion unit formed in a pixel region and configured to convert light into electrical charge. Further, the imaging element includes a transistor formed in the pixel region and configured to transfer electric charge from the photoelectric conversion unit. The photoelectric conversion unit of the imaging element may be connected to a well of the pixel region, where the well of the pixel region has a negative potential.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Applicant: SONY CORPORATION
    Inventors: Yosuke UENO, Yusuke IKEDA, Shizunori MATSUMOTO, Tsutomu HARUTA, Rei YOSHIKAWA
  • Publication number: 20200021769
    Abstract: The present technology is provided to accurately correct uneven luminance while suppressing an increase in the size of the solid-state imaging element. A pixel array unit includes a plurality of lines each including a predetermined number of pixels each being arrayed in a predetermined direction. An analog-to-digital conversion unit includes more than the predetermined number of analog-to-digital converters that convert analog signals into digital signals. A scanning circuit controls to sequentially select the plurality of lines and output more than the predetermined number of analog signals to the analog-to-digital conversion unit every time the line is selected. A correction unit performs black level correction processing on the digital signal.
    Type: Application
    Filed: October 27, 2017
    Publication date: January 16, 2020
    Inventors: ATSUMI NIWA, SHIZUNORI MATSUMOTO, EIJI HIRATA
  • Patent number: 10529756
    Abstract: An imaging element comprises a photoelectric conversion unit formed in a pixel region and configured to convert light into electrical charge. Further, the imaging element includes a transistor formed in the pixel region and configured to transfer electric charge from the photoelectric conversion unit. The photoelectric conversion unit of the imaging element may be connected to a well of the pixel region, where the well of the pixel region has a negative potential.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: January 7, 2020
    Assignee: Sony Corporation
    Inventors: Yosuke Ueno, Yusuke Ikeda, Shizunori Matsumoto, Tsutomu Haruta, Rei Yoshikawa
  • Publication number: 20190297293
    Abstract: The present disclosure relates to a solid-state image sensing apparatus, a control method, and an electronic device capable of reducing a settling time of a vertical signal line at the time of a read operation of pixels. A column processing unit A/D converts pixel signals of a plurality of pixels. A vertical signal line feeds the pixel signals output from the pixels to the A/D converter. A pull-up circuit increases a potential of the vertical signal line at the time of starting a read operation of the pixels. For example, the present disclosure can be applied to a CMOS (Complementary Metal-Oxide Semiconductor) image sensor that performs an interleaving operation or the like.
    Type: Application
    Filed: June 12, 2019
    Publication date: September 26, 2019
    Applicant: Sony Corporation
    Inventors: Shizunori Matsumoto, Pawankumar Pradeepkumar Moyade
  • Publication number: 20190288029
    Abstract: To prevent a decline in image quality by reducing a fluctuation in an image signal that is based on a fluctuation in a voltage of a negative voltage power source. An image signal output unit is controlled in accordance with a first control signal indicating either voltage state of an on voltage for causing a conductive state and an off voltage having a polarity different from that of the on voltage, and outputs an analog image signal corresponding to the electric charge held by an electric charge holding unit in the conductive state. A reset unit is controlled in accordance with a second control signal indicating either voltage state of the on voltage and the off voltage, resets the electric charge holding unit in the conductive state, transmits a fluctuation in the off voltage to the electric charge holding unit, and fluctuates the analog image signal.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 19, 2019
    Inventors: TATSUKI NISHINO, YOSUKE UENO, YUSUKE MORIYAMA, SHIZUNORI MATSUMOTO
  • Patent number: 10368026
    Abstract: The present disclosure relates to a solid-state image sensing apparatus, a control method, and an electronic device capable of reducing a settling time of a vertical signal line at the time of a read operation of pixels. A column processing unit A/D converts pixel signals of a plurality of pixels. A vertical signal line feeds the pixel signals output from the pixels to the A/D converter. A pull-up circuit increases a potential of the vertical signal line at the time of starting a read operation of the pixels. For example, the present disclosure can be applied to a CMOS (Complementary Metal-Oxide Semiconductor) image sensor that performs an interleaving operation or the like.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 30, 2019
    Assignee: Sony Corporation
    Inventors: Shizunori Matsumoto, Pawankumar Pradeepkumar Moyade
  • Patent number: 10356345
    Abstract: The present technology relates to a solid-state imaging device, an electronic apparatus, and an AD converter that are capable of suppressing the occurrence of an error in AD conversion results. The solid-state imaging device includes a pixel section having a plurality of pixels, a comparator for comparing a pixel signal outputted from the pixels with a reference signal, and a counter for counting the time of comparison made by the comparator. The comparator includes a first amplifier for comparing the pixel signal with the reference signal, a second amplifier that has a first transistor and amplifies an output signal of the first amplifier, and a second transistor having the same polarity as the first transistor. A gate of the second transistor is connected to an output end of the first amplifier, and a source and a drain of the second transistor are connected to the same fixed potential as a source of the first transistor. The present technology is applicable, for example, to a CMOS image sensor.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Sony Corporation
    Inventors: Katsuhiko Hanzawa, Shizunori Matsumoto
  • Patent number: 10298861
    Abstract: The present technology relates to a solid-state imaging device, an electronic apparatus, and an AD converter that are capable of suppressing the occurrence of an error in AD conversion results. The solid-state imaging device includes a pixel section having a plurality of pixels, a comparator for comparing a pixel signal outputted from the pixels with a reference signal, and a counter for counting the time of comparison made by the comparator. The comparator includes a first amplifier for comparing the pixel signal with the reference signal, a second amplifier that has a first transistor and amplifies an output signal of the first amplifier, and a second transistor having the same polarity as the first transistor. A gate of the second transistor is connected to an output end of the first amplifier, and a source and a drain of the second transistor are connected to the same fixed potential as a source of the first transistor. The present technology is applicable, for example, to a CMOS image sensor.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: May 21, 2019
    Assignee: Sony Corporation
    Inventors: Katsuhiko Hanzawa, Shizunori Matsumoto
  • Patent number: 10250836
    Abstract: The present disclosure relates to a solid-state image sensing apparatus, a control method, and an electronic device capable of reducing a settling time of a vertical signal line at the time of a read operation of pixels. A column processing unit A/D converts pixel signals of a plurality of pixels. A vertical signal line feeds the pixel signals output from the pixels to the A/D converter. A pull-up circuit increases a potential of the vertical signal line at the time of starting a read operation of the pixels. For example, the present disclosure can be applied to a CMOS (Complementary Metal-Oxide Semiconductor) image sensor that performs an interleaving operation or the like.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: April 2, 2019
    Assignee: Sony Corporation
    Inventors: Shizunori Matsumoto, Pawankumar Pradeepkumar Moyade