Patents by Inventor Shogo Mochizuki

Shogo Mochizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates
    Patent number: 10170620
    Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Forming strained channel with germanium condensation
    Patent number: 10164103
    Abstract: A method for forming a semiconductor device includes forming a strained fin on a substrate, a sacrificial gate on a channel region of the fin, a first spacer adjacent to a sidewall of the fin, and a second spacer adjacent to the first spacer. A source/drain region is grown on an exposed portion of the fin. Atoms are driven from the source/drain region into the fin and form an oxide layer on the source/drain region. The second spacer and the oxide layer are removed. An insulator layer is formed over the source/drain region, and the sacrificial gate is removed to expose the channel region of the fin. A gate stack is formed over the channel region of the fin.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shogo Mochizuki, Jie Yang
  • FORMING STRAINED CHANNEL WITH GERMANIUM CONDENSATION
    Publication number: 20180358460
    Abstract: A method for forming a semiconductor device includes forming a strained fin on a substrate, a sacrificial gate on a channel region of the fin, a first spacer adjacent to a sidewall of the fin, and a second spacer adjacent to the first spacer. A source/drain region is grown on an exposed portion of the fin. Atoms are driven from the source/drain region into the fin and form an oxide layer on the source/drain region. The second spacer and the oxide layer are removed. An insulator layer is formed over the source/drain region, and the sacrificial gate is removed to expose the channel region of the fin. A gate stack is formed over the channel region of the fin.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Inventors: Kangguo Cheng, Shogo Mochizuki, Jie Yang
  • VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS HAVING DIFFERENT CHANNEL LENGTHS
    Publication number: 20180358269
    Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.
    Type: Application
    Filed: April 26, 2018
    Publication date: December 13, 2018
    Inventors: Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki, Chun W. Yeung
  • SELF-ALIGNED AIR GAP SPACER FOR NANOSHEET CMOS DEVICES
    Publication number: 20180358435
    Abstract: A semiconductor structure is provided that contains a plurality of vertically stacked and spaced apart semiconductor nanosheets in which an inner dielectric liner and an air gap are present. Collectively, each inner spacer and air gap combination provides an inner spacer structure that separates a portion of a functional gate structure that surrounds each semiconductor nanosheet from a portion of a source/drain (S/D) semiconductor material structure that is present on each side of the functional gate structure.
    Type: Application
    Filed: November 14, 2017
    Publication date: December 13, 2018
    Inventors: Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin, Junli Wang
  • FINFET WITH SIGMA RECESSED SOURCE/DRAIN AND UN-DOPED BUFFER LAYER EPITAXY FOR UNIFORM JUNCTION FORMATION
    Publication number: 20180358465
    Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
    Type: Application
    Filed: November 9, 2017
    Publication date: December 13, 2018
    Inventors: Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh
  • VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS HAVING DIFFERENT CHANNEL LENGTHS
    Publication number: 20180358268
    Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.
    Type: Application
    Filed: April 26, 2018
    Publication date: December 13, 2018
    Inventors: Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki, Chun W. Yeung
  • Vertical transistor device
    Patent number: 10141426
    Abstract: According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity. The method also includes performing an isotropic etching process to remove portions of the semiconductor substrate in the first cavity and form a first undercut region below the liner layer, growing a first epitaxial semiconductor material in the first undercut region and the first cavity, and performing a first annealing process to drive dopants from the first epitaxial semiconductor material into the first fin to form a first source/drain layer under the first fin and in portions of the semiconductor substrate.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACAHINES CORPORATION
    Inventors: Brent A. Anderson, Huiming Bu, Fee Li Lie, Shogo Mochizuki, Junli Wang
  • BOTTOM CONTACT RESISTANCE REDUCTION ON VFET
    Publication number: 20180337277
    Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.
    Type: Application
    Filed: February 27, 2018
    Publication date: November 22, 2018
    Inventors: Ruqiang Bao, ChoongHyun Lee, Shogo Mochizuki, Hemanth Jagannathan
  • Gate top spacer for finFET
    Patent number: 10134763
    Abstract: The capacitance between gate structures and source/drain contacts of FinFET devices is reduced by the incorporation of inner spacers in the top portions of the gate structures. A replacement metal gate process used in the fabrication of such devices includes formation of the inner spacers following partial removal of dummy gate material. The remaining dummy gate material is then removed and replaced with gate dielectric and metal gate material.
    Type: Grant
    Filed: December 31, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • SELF ALIGNED TOP EXTENSION FORMATION FOR VERTICAL TRANSISTORS
    Publication number: 20180331216
    Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.
    Type: Application
    Filed: July 24, 2018
    Publication date: November 15, 2018
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Bottom contact resistance reduction on VFET
    Patent number: 10128372
    Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, ChoongHyun Lee, Shogo Mochizuki, Hemanth Jagannathan
  • Forming a contact for a semiconductor device
    Patent number: 10115824
    Abstract: A method for fabricating a semiconductor device includes forming a gate stack on a semiconductor substrate, forming a source/drain region on an exposed portion of the substrate, and forming a semiconductor material layer on the source/drain region. A first liner layer is deposited on the semiconductor material layer, and a second liner layer is deposited on the first liner layer. A conductive contact material is deposited on the second liner layer.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Ruilong Xie
  • MIS CAPACITOR FOR FINNED SEMICONDUCTOR STRUCTURE
    Publication number: 20180308993
    Abstract: MIS capacitors are formed using a finned semiconductor structure. A highly doped region including the fins is formed within the structure and forms one plate of a MIS capacitor. A metal layer forms a second capacitor plate that is separated from the first plate by a high-k capacitor dielectric layer formed directly on the highly doped fins. Contacts are electrically connected to the capacitor plates. A highly doped implantation layer having a conductivity type opposite to that of the highly doped region provides electrical isolation within the structure.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 25, 2018
    Inventors: Keith E. Fogel, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
  • GATE METAL PATTERNING FOR TIGHT PITCH APPLICATIONS
    Publication number: 20180308768
    Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.
    Type: Application
    Filed: June 16, 2018
    Publication date: October 25, 2018
    Inventors: Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin, Junli Wang
  • GATE METAL PATTERNING FOR TIGHT PITCH APPLICATIONS
    Publication number: 20180308767
    Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.
    Type: Application
    Filed: June 16, 2018
    Publication date: October 25, 2018
    Inventors: Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin, Junli Wang
  • GATE METAL PATTERNING FOR TIGHT PITCH APPLICATIONS
    Publication number: 20180308766
    Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.
    Type: Application
    Filed: April 25, 2017
    Publication date: October 25, 2018
    Inventors: Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin, Junli Wang
  • Gate metal patterning for tight pitch applications
    Patent number: 10103065
    Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin, Junli Wang
  • VTFET DEVICES UTILIZING LOW TEMPERATURE SELECTIVE EPITAXY
    Publication number: 20180294354
    Abstract: Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.
    Type: Application
    Filed: June 13, 2018
    Publication date: October 11, 2018
    Inventors: HEMANTH JAGANNATHAN, SHOGO MOCHIZUKI
  • FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation
    Patent number: 10096713
    Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh