Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

Abstract: A method of forming gate structures to a nanosheet device that includes forming at least two stacks of nanosheets, wherein each nanosheet includes a channel region portion having a gate dielectric layer present thereon. The method may further include forming a dual metal layer scheme on the gate dielectric layer of each nanosheet. The dual metal layer scheme including an etch stop layer of a first composition and a work function adjusting layer of a second composition, wherein the etch stop layer has a composition that provides that the work function adjusting layer is removable by a wet etch chemistry that is selective to the etch stop layer.

Abstract: A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.

Abstract: A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.

Abstract: A semiconductor structure is provided in which gallium-doped sacrificial epitaxial or polycrystalline germanium layer is formed on a silicon germanium substrate having a high percentage of germanium followed by annealing to diffuse the gallium into the silicon germanium substrate. The germanium layer is selectively removed to expose the surface of a gallium-doped silicon germanium region within the silicon germanium substrate. The process has application to the formation of electrically conductive regions within integrated circuits such as source/drain regions and junctions without the introduction of carbon into such regions.

Abstract: Techniques for forming VFETs having different gate lengths (and optionally different gate pitch and/or gate oxide thickness) on the same wafer are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a wafer including a first fin(s) patterned to a first depth and a second fin(s) patterned to a second depth, wherein the second depth is greater than the first depth; forming bottom source/drains at a base of the fins; forming bottom spacers on the bottom source/drains; forming gates alongside the fins, wherein the gates formed alongside the first fin(s) have a first gate length Lg1, wherein the gates formed alongside the second fin(s) have a second gate length Lg2, and wherein Lg1<Lg2; forming top spacers over the gates; and forming top source/drains over the top spacers. A VFET is also provided.

Abstract: A technique relates to fabricating a semiconductor device. A contact trench is formed in an inter-level dielectric layer. The contact trench creates an exposed portion of a semiconductor substrate through the inter-level dielectric layer. A gate stack is on the semiconductor substrate, and the inter-level dielectric layer is adjacent to the gate stack and the semiconductor substrate. A source/drain region is formed in the contact trench such that the source/drain region is on the exposed portion of the semiconductor substrate. Tin is introduced in the source/drain region to form an alloyed layer on top of the source/drain region, and the alloyed layer includes the tin and a source/drain material of the source/drain region. A trench layer is formed in the contact trench such that the trench layer is on top of the alloyed layer. A metallic liner layer is formed on the trench layer and the inter-level dielectric layer.

Abstract: A vertical field-effect transistor (FET) device is fabricated with a self-aligned bottom insulating spacer for improved electrostatic control. A semiconductor fin is formed on a semiconductor substrate. A lower source/drain region, which is formed of a first type of epitaxial semiconductor material, is epitaxially grown on a surface of the substrate in contact with a bottom portion of the semiconductor fin. A sacrificial epitaxial semiconductor layer is epitaxially grown on top of the lower source/drain region, wherein the sacrificial epitaxial semiconductor layer is formed of a second type of epitaxial semiconductor material which is different from the first type of epitaxial semiconductor material. The sacrificial epitaxial semiconductor layer is selectively oxidized to form a self-aligned bottom insulating spacer comprising an oxide layer. A gate structure is formed contact with sidewalls of the semiconductor fin.

Abstract: In an embodiment, this invention relates to a vertical field-effect transistor component including a bottom source-drain layer and a method of creating the same. The method of forming a bottom source-drain layer of a vertical field-effect transistor component can comprise forming an anchor structure on a substrate. A sacrificial layer can be deposited on a middle region of the substrate and a channel layer can be deposited on the sacrificial layer. A plurality of vertical fins can be formed on the substrate and the sacrificial layer can be removed such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate. The bottom source-drain layer can then be formed such that the bottom source-drain layer fills in the gap.

Abstract: A method for forming a semiconductor device includes forming a strained fin on a substrate, a sacrificial gate on a channel region of the fin, a first spacer adjacent to a sidewall of the fin, and a second spacer adjacent to the first spacer. A source/drain region is grown on an exposed portion of the fin. Atoms are driven from the source/drain region into the fin and form an oxide layer on the source/drain region. The second spacer and the oxide layer are removed. An insulator layer is formed over the source/drain region, and the sacrificial gate is removed to expose the channel region of the fin. A gate stack is formed over the channel region of the fin.

Abstract: A vertical FET structure includes a bottom source-drain region disposed on a substrate of the first type; a recessed first heterostructure layer disposed on the bottom source-drain region; a first fin disposed on the bottom source-drain region; a dielectric inner spacer disposed on the recessed first heterostructure; an outer spacer disposed on the inner spacer; a high-k and metal gate layer disposed on the outer spacer, the inner spacer, and the channel layer; an interlayer dielectric oxide disposed between the first fin and the outer spacer; a recessed second heterostructure layer disposed on top of the substrate of the first type and high-k and metal gate layer; a dielectric inner spacer disposed on the recessed second heterostructure layer; and a top source-drain region layer disposed on the dielectric inner spacer and recessed second heterostructure layer resulting in the vertical FET. A method for forming the vertical FET is also provided.

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a first trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.

Abstract: A nanosheet transistor device having reduced access resistance is fabricated by recessing channel nanosheets and replacing the channel material with epitaxially grown doped extension regions. Sacrificial semiconductor layers between the channel nanosheets are selectively removed without damaging source/drain regions epitaxially grown on the extension regions. The sacrificial semiconductor layers are replaced by gate dielectric and gate metal layers.

Abstract: A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

Abstract: In an embodiment, this invention relates to a vertical field-effect transistor component including a bottom source-drain layer and a method of creating the same. The method of forming a bottom source-drain layer of a vertical field-effect transistor component can comprise forming an anchor structure on a substrate. A sacrificial layer can be deposited on a middle region of the substrate and a channel layer can be deposited on the sacrificial layer. A plurality of vertical fins can be formed on the substrate and the sacrificial layer can be removed such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate. The bottom source-drain layer can then be formed such that the bottom source-drain layer fills in the gap.

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeOx) from the second interfacial layer by applying a combination of hydrogen (H2) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeOx) and removal of the GeOx results in formation of a pure silicon dioxide (SiO2) layer.

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

Abstract: A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.