Abstract: A solid-state imaging device includes a semiconductor region of p-type; a buried region of n-type, configured to serve as a photodiode together with the semiconductor region; a extraction region of n-type, configured to extract charges generated by the photodiode from the buried region, having higher impurity concentration than the buried region; a read-out region of n-type, configured to accumulate charges, which are transferred from the buried region having higher impurity concentration than the buried region; and a potential gradient changing mechanism, configured to control a potential of the channel, and to change a potential gradient of a potential profile from the buried region to the read-out region and a potential gradient of a potential profile from the buried region to the extraction region, so as to control the transferring/extraction of charges.

Abstract: A semiconductor element encompasses a charge-transfer path defined in a semiconductor region (34.35), configured to transfer signal charges, (b) a pair of first field-control electrodes (42a, 42b) laminated via an insulating film on the semiconductor region so as to sandwich the charge-transfer path in between, and a pair of second field-control electrodes (43a, 43b) arranged separately from and adjacently to the first field-control electrodes (42a, 42b). By applying field-control voltages differing from each other, to the first and second field-control electrodes (43a, 43b), a depleted potential in the charge-transfer path is changed, and a movement of the signal charges transferring in the semiconductor region is controlled. Because electric field can be made constant over a long distance along the charge-transfer direction, a semiconductor element and a solid-state imaging device, in which problems caused by interface defects and the like are avoided, can be provided.

Abstract: An image sensor controls the gain of a pixel signal on a pixel-by-pixel basis and extends a dynamic range while maintaining a S/N ratio at a favorable level. A column unit in an image sensor is independently detects a level of each pixel signal and independently sets a gain for level of the signal. A photoelectric converting region unit has pixels arranged two-dimensionally with a vertical signal line for each pixel column to output each pixel signal. The column unit is on an output side of the vertical signal line. The column unit for each pixel column has a pixel signal level detecting circuit, a programmable gain control, a sample and hold (S/H) circuit. Gain correction is performed according to a result of a detected level of the pixel signal.

Abstract: A solid-state image pickup device 1A includes an image pickup section 2 having a pixel array P in which a pixel C is two-dimensionally arranged, a lens section 3 having a plurality of lenses 3a arranged on the pixel array P, and an image generating section 4A for generating an image by using an electrical signal SE. The image pickup section 2 has a plurality of the pixel arrays P including one image pickup region T. The image generating section 4A generates the image by averaging the electrical signals SE for each pixel C corresponding to one another among the image pickup regions T, in order to reduce noise present in the electrical signal SE.

Abstract: A pre-amplifier (column region unit) of a solid-state imaging device including a pixel-signal controller. The pixel-signal controller, for each vertical signal line, detects the level of each pixel signal independently by a pixel-signal detector on the output side of a pixel-signal amplifier, and sets a gain independently to the pixel-signal amplifier according to the level of the signal. At a subsequent stage of the solid-state imaging device, an analog-to-digital (A/D) converter and a signal extending unit are provided. The A/D converter digitizes a pixel signal, and the digitized pixel signal is corrected by a gain set to the pixel-signal amplifier with reference to a classification signal from the pixel-signal detector, so that the dynamic range of signals of one screen is extended.

Abstract: A semiconductor element encompasses a charge-transfer path defined in a semiconductor region (34.35), configured to transfer signal charges, (b) a pair of first field-control electrodes (42a, 42b) laminated via an insulating film on the semiconductor region so as to sandwich the charge-transfer path in between, and a pair of second field-control electrodes (43a, 43b) arranged separately from and adjacently to the first field-control electrodes (42a, 42b). By applying field-control voltages differing from each other, to the first and second field-control electrodes (43a, 43b), a depleted potential in the charge-transfer path is changed, and a movement of the signal charges transferring in the semiconductor region is controlled. Because electric field can be made constant over a long distance along the charge-transfer direction, a semiconductor element and a solid-state imaging device, in which problems caused by interface defects and the like are avoided, can be provided.

Abstract: A optical-information acquisition element encompasses a semiconductor layer (31) of a p-type, a surface-buried region (33) of a n-type buried in the semiconductor layer (31) so as to implement a photodiode with the semiconductor layer (31), a charge-accumulation region (36) of the n-type buried in the surface-buried region (33), configured to accumulate charges generated by the photodiode, a barrier-creating region of the p-type buried in the surface-buried region (33) so as to sandwich the surface-buried region (33) with the semiconductor layer (31), configured to create a potential barrier, and a charge-exhaust region (34) of the n-type buried in the semiconductor layer (31), configured to store and to extract excess charges which surmount the potential barrier and flow out from the charge-accumulation region (36). The changes of potential level of the charge-accumulation region (36) are extracted as signals, after receiving optical-communication signals.

Abstract: At least one cell implementing a sensor array embraces a photoelectric-conversion accumulation element configured to generate and accumulate signal charges, a potential detection circuit configured to detect the signal charges generated by the photoelectric-conversion accumulation element as a potential change, and an amplification circuit configured to amplify the potential change and to transmit to an output-signal line. The photoelectric-conversion accumulation element and the potential detection circuit are connected in series between a first potential terminal and a second potential terminal, and the potential detection circuit has an insulated-gate transistor, which detects the potential change in a weak inversion state, in a period when an optical-communication signal is received.

Abstract: A ramp signal generation circuit 21 comprises a plurality of unit circuits 221 to 22N, each including a capacitor 26 having one end 26a held at a fixed potential and a current source 27 connected to the other end 26b of the capacitor 26, while the other ends 26b of the capacitors 26 in the plurality of unit circuits 221 to 22N are connected to each other with a wiring member W.

Abstract: A pixel 10 includes a photodiode PD which is provided between a first barrier region 21 forming a first potential barrier B1 and a second barrier region 27 forming a second potential barrier B2, a first floating diffusion region F1 which is provided adjacent to the first barrier region 21, and to which a first electric charge generated in the photodiode PD is transferred, and a second floating diffusion region F2 which is provided adjacent to the second barrier region 27, and into which a second electric charge generated in the photoelectric conversion region PD flows, and in which a part of the flowing-in second electric charge is accumulated. The second potential barrier B2 is lower than the first potential barrier B1.

Abstract: An image sensor controls the gain of a pixel signal on a pixel-by-pixel basis and extends a dynamic range while maintaining a S/N ratio at a favorable level. A column unit in an image sensor is independently detects a level of each pixel signal and independently sets a gain for level of the signal. A photoelectric converting region unit has pixels arranged two-dimensionally with a vertical signal line for each pixel column to output each pixel signal. The column unit is on an output side of the vertical signal line. The column unit for each pixel column has a pixel signal level detecting circuit, a programmable gain control, a sample and hold (S/H) circuit. Gain correction is performed according to a result of a detected level of the pixel signal.

Abstract: In a pixel 11, a floating semiconductor region FD accumulates a charge from a photoelectric transducer PD. A first charge transfer path CTP1 extends from the photoelectric transducer PD to the floating semiconductor region FD through the storage diode SD. A second charge transfer path CTP2 extends from the photoelectric transducer PD to the floating semiconductor region. An output unit AMP provides a signal corresponding to a potential in the floating semiconductor region FD. The first charge transfer path CTP includes a first shutter switch TR(GS1) for controlling a transfer of the charge from the photoelectric transducer PD, the storage diode SD for accumulating the charge from the photoelectric transducer PD, and a transfer switch TR(TF1) for controlling a transfer of the charge from the storage diode SD to the floating semiconductor region PD, while the second charge transfer path CTP includes a shutter switch TR(GS2) for controlling a transfer of the charge from the photoelectric transducer PD.

Abstract: Charge generated in a photodiode is properly split for difference processing. An imaging element is constituted by a semiconductor such that a charge accumulation portion is connected to a light receiving portion using a buried photodiode and charge is split from the charge accumulation portion by a plurality of gates and is accumulated. An imaging device includes a control device performing control so as to accumulate charge that is generated by a photoelectric conversion at an exposure cycle synchronous with the light emission of a light source. The exposure cycle includes a first period for receiving reflection light from a subject illuminated by light from the light source and a second period for receiving light from the subject illuminated by an environmental light not including the light from the light source.

Abstract: A pre-amplifier (column region unit) of a solid-state imaging device including a pixel-signal controller. The pixel-signal controller, for each vertical signal line, detects the level of each pixel signal independently by a pixel-signal detector on the output side of a pixel-signal amplifier, and sets a gain independently to the pixel-signal amplifier according to the level of the signal. At a subsequent stage of the solid-state imaging device, an analog-to-digital (A/D) converter and a signal extending unit are provided. The A/D converter digitizes a pixel signal, and the digitized pixel signal is corrected by a gain set to the pixel-signal amplifier with reference to a classification signal from the pixel-signal detector, so that the dynamic range of signals of one screen is extended.

Abstract: An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to ½L that in the A/D converter circuit 103.

Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

Abstract: According to this A/D converter, a first A/D conversion operation for performing integral A/D conversion and a second A/D conversion operation for performing cyclic A/D conversion are realized based on control of operational procedures in a same circuit configuration. Moreover, in the first A/D conversion operation, since a capacity of a capacitor used in the integration of an output signal is greater than a capacity of a capacitor used for storing an input analog signal and a standard reference voltage, the analog signal that is input in the integral A/D conversion is attenuated according to the capacity ratio and subject to sampling and integration. Consequently, the voltage range of the analog signal that is output in the integral A/D conversion also decreases according to the capacity ratio of the capacitors, and the A/D converter can be therefore constructed with a single-ended configuration.

Abstract: An A/D conversion integrated circuit including a plurality of A/D converters which can inhibit noises from being propagated by capacitive coupling from a conductor which transmits a digital signal is provided. In an A/D converter 13, an input 15 receives an analog signal to be A/D converted. An output 17 provides at least a part of a digital signal SD having a predetermined number of bits representing the analog signal SA. In response to an analog signal SA, a sub-A/D conversion circuit 19 generates a signal SDP representing one or a plurality of bit values of the digital signal SD and feeds the signal SDP to the output 17. An input 21a of a control circuit 21 is connected to an output 19a of the sub-A/D conversion circuit 19 and provides a control signal SCONT corresponding to the signal SDP. The control signal SCONT has a waveform including a transition from a voltage level L1 to a voltage level L2 and a transition from the voltage level L2 to the voltage level L1.

Abstract: A sensor circuit integrated with a signal processing circuit and a charging circuit. The sensor circuit has a sensor voltage source to which a sensor internal resonance is connected in series, the signal processing circuit having a capacitor to which the sensor voltage source is connected via a signal line of the charging circuit, and a switch. The charging circuit includes another capacitor connected to the signal line, and a drive circuit at an input side of which the other capacitor is connected and which has a transconductance equivalent to an internal resistance.

Abstract: The present invention provides a high-speed charge-transfer photodiode encompassing a first conductivity type semiconductor layer (20) serving as a charge-generation region; and a second conductivity type surface-buried region (21a) serving as a charge-transfer region of charges generated by the charge-generation region, wherein a specified direction in the surface-buried region (21a) provided along a plane parallel to a surface of the semiconductor layer (20) is assigned as a charge-transfer direction of the charges, and at least one of a variation of widths of the surface-buried region (21a) measured in an orthogonal direction to the charge-transfer direction and a variation of impurity concentration distributions of the surface-buried region (21a), which are measured along the charge-transfer direction, is determined such that an electric field distribution in the charge-transfer direction is constant.