Abstract: A cyclic A/D converter which can reduce the number of reference voltages for D/A conversion is provided. The cyclic A/D converter (11) comprises a gain stage (15), an A/D converter circuit (17), a logic circuit (19), and a D/A converter circuit (21). In an operational action of the gain stage (15), an operational value (VOP) is generated by the use of an operational amplifier circuit (23) and capacitors (25, 27, 29). The gain stage (15) operates as receiving three kinds of voltage signal from the D/A converter circuit (21) by the switching of two kinds of voltage signal (VDA1, VDA2) to be applied to the capacitors (25, 27) in a switching circuit (31).

Abstract: An image sensor controls the gain of a pixel signal on a pixel-by-pixel basis and extends a dynamic range while maintaining a S/N ratio at a favorable level. A column unit in an image sensor is independently detects a level of each pixel signal and independently sets a gain for level of the signal. A photoelectric converting region unit has pixels arranged two-dimensionally with a vertical signal line for each pixel column to output each pixel signal. The column unit is on an output side of the vertical signal line. The column unit for each pixel column has a pixel signal level detecting circuit, a programmable gain control, a sample and hold (S/H) circuit. Gain correction is performed according to a result of a detected level of the pixel signal.

Abstract: A semiconductor element includes a base-body region of p-type; a charge-generation buried region of a n-type, implementing a photodiode together with the base-body region, configured to create a first potential valley in the base-body region; an accumulation region of n-type, being buried in a part of the upper portion of the base-body region, configured to create a second potential valley deeper than the first potential valley; a transfer-gate insulation film provided on a surface of the base-body region; a transfer-gate electrode provided on the transfer-gate insulation film, configured to control a potential of a transfer channel formed in the base-body region between the charge-generation buried region and the accumulation region; and a recessed-potential creation mechanism configured to create a stair-like-shaped potential barrier for electronic shuttering.

Abstract: An A/D converter 11 performs multiple-times sampling on a first signal S1 in a first period T1 while performing multiple-times sampling on a second signal S2 in a second period T2. An A/D converter circuit 17 provides a digital signal in response to a signal from an output 15b of a gain stage 15 in the second period T2. The digital signal may have a value “1” or a value “0”. The A/D converter circuit 17 includes a circuit 18 providing a signal SA/DM corresponding to the number of times the value “1” appears. A switch 24 operates in response to a clock signal ?s and is used to sample a signal from a pixel 2a. In a first capacitor circuit 27, a switch 29 and a capacitor 31 are connected to an inverting input 23a and a non-inverting output 23b, respectively. The switch 29 operates in response to a clock signal ?3 and is used for integration in the capacitor 31.

Abstract: A distance image sensor capable of enlarging the distance measurement range without reducing the distance resolution is provided. A radiation source 13 provides first to fifth pulse trains PT1 to PT5 which are irradiated to the object as radiation pulses in the first to fifth frames arranged in order on a time axis. In each of the frames, imaging times TPU1 to TPU5 are prescribed at points of predetermined time ?TPD from the start point of each frame, also the pulses PT1 to PT5 are shifted respectively by shift amounts different from each other from the start point of the first to fifth frames. A pixel array 23 generates element image signals SE1 to SE5 each of which has distance information of an object in distance ranges different from each other using imaging windows A and B in each of five frames. A processing unit 17 generates an image signal SIMAGE by combining the element image signals.

Abstract: An image sensor controls the gain of a pixel signal on a pixel-by-pixel basis and extends a dynamic range while maintaining a S/N ratio at a favorable level. A column unit in an image sensor is independently detects a level of each pixel signal and independently sets a gain for level of the signal. A photoelectric converting region unit has pixels arranged two-dimensionally with a vertical signal line for each pixel column to output each pixel signal. The column unit is on an output side of the vertical signal line. The column unit for each pixel column has a pixel signal level detecting circuit, a programmable gain control, a sample and hold (S/H) circuit. Gain correction is performed according to a result of a detected level of the pixel signal.

Abstract: An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to ½L that in the A/D converter circuit 103.

Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

Abstract: In a pixel 11, a floating semiconductor region FD accumulates a charge from a photoelectric transducer PD. A first charge transfer path CTP1 extends from the photoelectric transducer PD to the floating semiconductor region FD through the storage diode SD. A second charge transfer path CTP2 extends from the photoelectric transducer PD to the floating semiconductor region. An output unit AMP provides a signal corresponding to a potential in the floating semiconductor region FD. The first charge transfer path CTP includes a first shutter switch TR(GS1) for controlling a transfer of the charge from the photoelectric transducer PD, the storage diode SD for accumulating the charge from the photoelectric transducer PD, and a transfer switch TR(TF1) for controlling a transfer of the charge from the storage diode SD to the floating semiconductor region PD, while the second charge transfer path CTP includes a shutter switch TR(GS2) for controlling a transfer of the charge from the photoelectric transducer PD.

Abstract: A semiconductor element includes: a p-type semiconductor region; an n-type light-receiving surface buried region buried in the semiconductor region; an n-type charge accumulation region buried in the semiconductor region, continuously to the light-receiving surface buried region, establishing a deeper potential well depth than the light-receiving surface buried region; a charge read-out region configured to read out the charges accumulated in the charge accumulation region; an exhaust-drain region buried in the semiconductor region, configured to extract the charges from the light-receiving surface buried region; a first potential controller configured to extract the charges from the light-receiving surface buried region to the exhaust-drain region; and a second potential controller configured to transfer the charges from the charge accumulation region to the charge read-out region.

Abstract: A optical-information acquisition element encompasses a semiconductor layer (31) of a p-type, a surface-buried region (33) of a n-type buried in the semiconductor layer (31) so as to implement a photodiode with the semiconductor layer (31), a charge-accumulation region (36) of the n-type buried in the surface-buried region (33), configured to accumulate charges generated by the photodiode, a barrier-creating region of the p-type buried in the surface-buried region (33) so as to sandwich the surface-buried region (33) with the semiconductor layer (31), configured to create a potential barrier, and a charge-exhaust region (34) of the n-type buried in the semiconductor layer (31), configured to store and to extract excess charges which surmount the potential barrier and flow out from the charge-accumulation region (36). The changes of potential level of the charge-accumulation region (36) are extracted as signals, after receiving optical-communication signals.

Abstract: A solid-state image pick-up device and a method of reading out a pixel signal thereof are provided, and the solid-state image pick-up device provides a large dynamic range without an increase in the area of a pixel. Plural pixels are arranged therein.

Abstract: A semiconductor range-finding element encompasses a semiconductor region (1), a light receiving surface-buried region (11a), a first charge-accumulation region (12a), a first charge read-out region (13), a first potential control means (31), a second potential control means (32), a first exhausting-drain region (14) and a third potential control means (33). The signal charges dependent on a delay time of the reflected light are repeatedly transferred from the light receiving surface-buried region (11a) to the first charge-accumulation region (12a) so as to be accumulated as a first signal charge in the first charge-accumulation region (12a) in a first repetition period, all of the signal charges generated by the reflected light are repeatedly transferred from the light receiving surface-buried region (11a) to the first charge-accumulation region (12a) so as to be accumulated as a second signal charge in the first charge-accumulation region (12a) in a second repetition period.

Abstract: A magnetic array sensor circuit to process an output from a magnetic sensor array including a plurality of magnetic sensor elements arranged in an array. The circuit includes a regulating circuit to reduce an offset variation of the output from the magnetic sensor elements arranged in the array. The regulating circuit includes a control circuit to operate the magnetic sensor element in a linear region. The control circuit includes a reference sensor element in the form of the magnetic sensor element short-circuited between two output terminals, a storage element to store a reference offset value read out from the reference sensor element, and a subtraction circuit to subtract the stored reference offset value from an output of the other magnetic sensor elements.

Abstract: An n-type region as a charge storage region of a photodiode is buried in a substrate. The interface between silicon and a silicon oxide film is covered with a high concentration p-layer and a lower concentration p-layer is formed only in the portion immediately below a floating electrode for signal extraction. Electrons generated by light are stored in the charge storage region, thereby changing the potential of the portion of the p-layer at the surface of the semiconductor region. The change is transmitted through a thin insulating film to the floating electrode by capacitive coupling and read out by a buffer transistor. Initialization of charges is executed by adding a positive high voltage to the gate electrode of a first transfer transistor such that the electrons stored in the charge storage region are transferred to the n+ region and generation of reset noise is protected.

Abstract: A semiconductor element includes a base-body region of p-type; a charge-generation buried region of a n-type, implementing a photodiode together with the base-body region, configured to create a first potential valley in the base-body region; an accumulation region of n-type, being buried in a part of the upper portion of the base-body region, configured to create a second potential valley deeper than the first potential valley; a transfer-gate insulation film provided on a surface of the base-body region; a transfer-gate electrode provided on the transfer-gate insulation film, configured to control a potential of a transfer channel formed in the base-body region between the charge-generation buried region and the accumulation region; and a recessed-potential creation mechanism configured to create a stair-like-shaped potential barrier for electronic shuttering.

Abstract: A solid-state imaging device includes a semiconductor region of p-type; a buried region of n-type, configured to serve as a photodiode together with the semiconductor region; a extraction region of n-type, configured to extract charges generated by the photodiode from the buried region, having higher impurity concentration than the buried region; a read-out region of n-type, configured to accumulate charges, which are transferred from the buried region having higher impurity concentration than the buried region; and a potential gradient changing mechanism, configured to control a potential of the channel, and to change a potential gradient of a potential profile from the buried region to the read-out region and a potential gradient of a potential profile from the buried region to the extraction region, so as to control the transferring/extraction of charges.

Abstract: An image sensor controls the gain of a pixel signal on a pixel-by-pixel basis and extends a dynamic range while maintaining a S/N ratio at a favorable level. A column unit in an image sensor is independently detects a level of each pixel signal and independently sets a gain for level of the signal. A photoelectric converting region unit has pixels arranged two-dimensionally with a vertical signal line for each pixel column to output each pixel signal. The column unit is on an output side of the vertical signal line. The column unit for each pixel column has a pixel signal level detecting circuit, a programmable gain control, a sample and hold (S/H) circuit. Gain correction is performed according to a result of a detected level of the pixel signal.

Abstract: An A/D conversion integrated circuit including a plurality of A/D converters which can inhibit noises from being propagated by capacitive coupling from a conductor which transmits a digital signal is provided. In an A/D converter 13, an input 15 receives an analog signal to be A/D converted. An output 17 provides at least a part of a digital signal SD having a predetermined number of bits representing the analog signal SA. In response to an analog signal SA, a sub-A/D conversion circuit 19 generates a signal SDP representing one or a plurality of bit values of the digital signal SD and feeds the signal SDP to the output 17. An input 21 a of a control circuit 21 is connected to an output 19a of the sub-A/D conversion circuit 19 and provides a control signal SCONT corresponding to the signal SDP. The control signal SCONT has a waveform including a transition from a voltage level L1 to a voltage level L2 and a transition from the voltage level L2 to the voltage level L1.

Abstract: A pre-amplifier (column region unit) of a solid-state imaging device including a pixel-signal controller. The pixel-signal controller, for each vertical signal line, detects the level of each pixel signal independently by a pixel-signal detector on the output side of a pixel-signal amplifier, and sets a gain independently to the pixel-signal amplifier according to the level of the signal. At a subsequent stage of the solid-state imaging device, an analog-to-digital (A/D) converter and a signal extending unit are provided. The A/D converter digitizes a pixel signal, and the digitized pixel signal is corrected by a gain set to the pixel-signal amplifier with reference to a classification signal from the pixel-signal detector, so that the dynamic range of signals of one screen is extended.