Abstract: An A/D converter comprises capacitors C1, C2, C3, C4, and C5 coupled via a plurality of switches to a differential input/differential output amplifier 1. The capacitor C5 determines a gain of the amplifier 1. A reset level is stored in the capacitor C1, and a signal level is stored in the capacitor C2. One terminal of the capacitor C1 and one terminal of the capacitor C2 are coupled to the respective differential inputs, and the other terminals of the capacitors C1, C2 are coupled to each other, whereby the amplifier 1 generates a difference signal between the reset level and the signal level. The cyclic A/D conversion of this difference signal is performed by switching the capacitors C1, C2, C3, and C4 coupled via a plurality of switches to the differential-input/differential-output amplifier 1, thereby obtaining an A/D conversion value with reduced random noise.

Abstract: To achieve an image sensor with low noise, small dark current and the high sensitivity, an n-type region serving as a charge storage region (2) of a photodiode is buried in a substrate (1). The interface between silicon and a silicon oxide film (4) is covered with a p-layer (3) of high concentration, and a p-layer (11) of a relatively low concentration is formed only in the portion immediately below a floating electrode (14) for signal extraction. The electrons generated by light are stored in the n-type region serving as the charge storage region (2), and the potential of the portion of the p-layer (11) at the surface of the semiconductor region is changed thereby. The change in the potential is transmitted through a thin insulating film to the floating electrode (14) in a floating state by the capacitive coupling. The change in the potential of the floating electrode (14) is read out by a buffer transistor (7).

Abstract: A distance image sensor for removing the background light and improving the charge transfer efficiency in a device for measuring the distance to an object by measuring the time-of-flight of the light. In a distance image sensor for determining the signals of two charge storage nodes which depend on the delay time of the modulated light, a signal by the background light is received from the third charge storage node or the two charge storage nodes in a period when the modulated light does not exist, and is subtracted from the signal which depends on the delay time of the two charge storage nodes, so as to remove the influence of the background. Also by using a buried diode as a photo-detector, and using an MOS gate as gate means, the charge transfer efficiency improves. The charge transfer efficiency is also improved by using a negative feedback amplifier where a capacitor is disposed between the input and output.

Abstract: To provide a rotation detecting apparatus capable of increasing the angle detecting precision without being affected by an offset signal resulting from a stress in a silicon chip, the rotation detecting apparatus 3 includes a magnetic sensor array 5 and a magnet 4 rotatable in face-to-face relation with the magnetic sensor array 5. The magnetic sensor array includes a plurality of groups 16 of sensor elements each group 16 including four sensor elements. The four sensor elements 5a to 5d of each combined sensor element group 16 are so arranged as to be oriented vertically and horizontally in four directions and connected parallel to each other.

Abstract: An A/D conversion array for an image sensor, in which the number of amplifiers and capacitors are decreased, compared with the conventional cyclic type, and a function to cancel the noise generated in the pixel section of the image sensor is provided, so that the area and power consumption are decreased. After input signal Vin is supplied to C1 and held, a reset level is applied to Vin, whereby the signal is amplified by the ratio of C1 and C2 (C1/C2). An output is held in C1, and the output is A/D-converted by a comparator so that a control signal is generated by the conversion output and a switch is turned ON. The digital signal is converted into an analog signal, and the analog signal is subtracted from the signal held in C1. This signal is amplified and is subjected to A/D conversion again, and the same operation is repeated.

Abstract: A lower cost range-finding image sensor based upon measurement of reflection time of light with reduced fabrication processes compared to standard CMOS manufacturing procedures. An oxide film is formed on a silicon substrate, and two photo-gate electrodes for charge-transfer are provided on the oxide film. Floating diffusion layers for taking charges out from a photodetector layer are provided at the ends of the oxide film, and on the outside thereof are provided a gate electrode for resetting and a diffusion layer for providing a reset voltage.

Abstract: In a conventional CMOS image sensor, an A/D converter for performing A/D conversion at high-speed arranges the A/D converter elements in columns so as to operate in parallel, and has low resolution in the order of 9 or so bits. The present invention provides an A/D converter for an image sensor, which performs a part of the A/D conversion functions by using a noise cancellation circuit in columns and performs amplification simultaneously with this, thereby obtaining a high signal noise ratio (SNR) and implementing an A/D converter with a high resolution along with the A/D conversion section in a subsequent stage.

Abstract: The present invention relates to a CMOS image sensor having a wide dynamic range, which permits favorable imaging even in cases where a bright portion and a dark portion exist simultaneously. The dynamic range can be widened by preventing the saturation of optical charge at a high illuminance by removing low illuminance signals due to long-time accumulation, intermediate illuminance signals due to short-time accumulation, and high illuminance signals due to ultra-short time accumulation from pixel portions of the image sensor. Further, adaptive control of the dynamic range can also be performed by dynamically changing the wide dynamic range imaging conditions that comprise a combination of different accumulation times of each of a plurality of short time accumulation signals.

Abstract: An A/D conversion array for an image sensor, in which the number of amplifiers and capacitors are decreased compared with the conventional cyclic type, and a function to cancel the noise generated in the pixel section of the image sensor is provided, so that the area and power consumption are decreased. After an input signal Vin is supplied to C1 and held, a reset level is applied to Vin, whereby the differential signal is amplified by the ratio of C1 and C2 (C1/C2) connected to an inverting amplifier. Then an output from the inverting amplifier is held in C1, and the output of the inverting amplifier is A/D-converted by a comparator so that a control signal is generated by the conversion output, and one of the switches controlled by ?M1, ?01 and ?P1 is turned ON. The digital signal is converted into an analog signal, and the analog signal is subtracted from the signal held in C1. This signal is amplified and is subjected to A/D conversion again, then the same operation is cyclically repeated.

Abstract: A distance image sensor for removing the background light and improving the charge transfer efficiency in a device for measuring the distance to an object by measuring the time-of-flight of the light. In a distance image sensor for determining the signals of two charge storage nodes which depend on the delay time of the modulated light, a signal by the background light is received from the third charge storage node or the two charge storage nodes in a period when the modulated light does not exist, and is subtracted from the signal which depends on the delay time of the two charge storage nodes, so as to remove the influence of the background. Also by using a buried diode as a photo-detector, and using an MOS gate as gate means, the charge transfer efficiency improves. The charge transfer efficiency is also improved by using a negative feedback amplifier where a capacitor is disposed between the input and output.

Abstract: In a conventional CMOS image sensor, an A/D converter for performing A/D conversion at high-speed arranges the A/D converter elements in columns so as to operate in parallel, and has low resolution in the order of 9 or so bits. The present invention provides an A/D converter for an image sensor, which performs a part of the A/D conversion functions by using a noise cancellation circuit in columns and performs amplification simultaneously with this, thereby obtaining a high signal noise ratio (SNR) and implementing an A/D converter with a high resolution along with the A/D conversion section in a subsequent stage.

Abstract: It is ideal to amplify voltage within a pixel to obtain sufficient sensitivity and low noise characteristics in a short storing time in order to acquire high-speed images, but no method has existed to satisfy the three requirements of the electronic shutter operation, removal of reset noise and signal voltage amplification. To solve this problem, the present invention takes the ratio of the capacitor C1 at point V1 and capacitor C2 at point V2 to be large, and transfers charges from V1 to V2, thereby enabling the signal voltage to be amplified. Moreover, the reset noise component sampled and included in VFD0 before opening TX is the same amount as the reset noise included in the voltage after TX is opened and the ?VFD of change occurred, so the reset noise is removed by taking out the amount of change ?VFD and amplifying the signal voltage. By returning R to 3V, the charge injection from the section V1 does not occur, thereby the voltage of V2 is held as is, and enters into storage status.

Abstract: A pre-amplifier (column region unit) of a solid-state imaging device includes a pixel-signal controller. The pixel-signal controller, for each vertical signal line, detects the level of each pixel signal independently by a pixel-signal detector on the output side of a pixel-signal amplifier, and sets a gain independently to the pixel-signal amplifier according to the level of the signal. At a subsequent stage of the solid-state imaging device, an analog-to-digital (A/D) converter and a signal extending unit are provided. The A/D converter digitizes a pixel signal, and the digitized pixel signal is corrected by a gain set to the pixel-signal amplifier with reference to a classification signal from the pixel-signal detector, so that the dynamic range of signals of one screen is extended.

Abstract: A master DLL circuit (3) generates a first delay signal (CKD) by delaying the master clock signal by a first delay time (T0) and generates a first pulse signal (Smp) having a pulse width (T0) of the first delay time, and generates a first control signal (Scp) which is changed in accordance with the first pulse signal (Smp), and adjusts the first delay time (T0) in accordance with the first control signal (Scp). Each slave DLL circuit (D1 to Dm) delays, by a second delay time (td), a delay internal clock signal, and outputs the delayed delay internal clock signals (CK1 to CKm) which form the multiphase clock signals. Each slave DLL circuit generates a second pulse signal (Ssp) having a pulse width (td) of the second delay time, and generates a second control signal (Scp1) which is changed in accordance with the first and second pulse signals (Smp, Ssp), and adjusts the second delay time (td) in accordance with the second control signal (Scp1), thus reducing a skew value of the multiphase clock signal.

Abstract: It is ideal to amplify voltage within a pixel to obtain sufficient sensitivity and low noise characteristics in a short storing time in order to acquire high-speed images, but no method has existed to satisfy the three requirements of the electronic shutter operation, removal of reset noise and signal voltage amplification. To solve this problem, the present invention takes the ratio of the capacitor C1 at point V1 and capacitor C2 at point V2 to be large, and transfers charges from V1 to V2, thereby enabling the signal voltage to be amplified. Moreover, the reset noise component sampled and included in VFD0 before opening TA is the same amount as the reset noise included in the voltage after TX is opened and the ?VFD of change occurred, so the reset noise is removed by taking out the amount of change ?VFD and amplifying the signal voltage. By returning R to 3V, the charge injection from the section V1 does not occur, thereby the voltage of V2 is held as is, and enters into storage status.

Abstract: A pseudo-differential amplifier circuit 1 is constructed from two equivalent amplifiers 2 and 3 that amplify a pair of input signals without using a differential pair. This pseudo-differential amplifier circuit 1 is used in an arithmetic unit in each of the A-D converter circuits AD1 through ADm in a parallel pipeline A-D converter 10.

Abstract: An image sensor controls the gain of a pixel signal on a pixel-by-pixel basis and extends a dynamic range while maintaining a S/N ratio at a favorable level. A column unit in an image sensor is independently detects a level of each pixel signal and independently sets a gain for level of the signal. A photoelectric converting region unit has pixels arranged two-dimensionally with a vertical signal line for each pixel column to output each pixel signal. The column unit is on an output side of the vertical signal line. The column unit for each pixel column has a pixel signal level detecting circuit, a programmable gain control, a sample and hold (S/H) circuit. Gain correction is performed according to a result of a detected level of the pixel signal.

Abstract: A master DLL circuit (3) generates a first delay signal (CKD) by delaying the master clock signal by a first delay time (T0) and generates a first pulse signal (Smp) having a pulse width (T0) of the first delay time, and generates a first control signal (Scp) which is changed in accordance with the first pulse signal (Smp), and adjusts the first delay time (T0) in accordance with the first control signal (Scp). Each slave DLL circuit (D1 to Dm) delays, by a second delay time (td), a delay internal clock signal, and outputs the delayed delay internal clock signals (CK1 to CKm) which form the multiphase clock signals. Each slave DLL circuit generates a second pulse signal (Ssp) having a pulse width (td) of the second delay time, and generates a second control signal (Scp1) which is changed in accordance with the first and second pulse signals (Smp, Ssp), and adjusts the second delay time (td) in accordance with the second control signal (Scp1), thus reducing a skew value of the multiphase clock signal.

Abstract: A sampling and hold circuit that can suppress voltage variation at the input terminals, which are virtual grounds, of a differential amplifier, depending on the frequency of input signals. During sampling operation, a serial circuit composed of a capacitor C1, to which a positive-side input voltage ViP is applied, and an NMOS transistor Q4, which is always turned on, is connected to an input terminal INP of a differential amplifier circuit 2. A serial circuit having the same impedance as that serial circuit and composed of a capacitor C3, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q9 is also connected to the input terminal INP. A serial circuit composed of a capacitor C2, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q5, which is always turned on, is connected to the other input terminal INM of a differential amplifier circuit 2.

Abstract: A sampling and hold circuit that can suppress voltage variation at the input terminals, which are virtual grounds, of a differential amplifier, depending on the frequency of input signals. During sampling operation, a serial circuit composed of a capacitor C1, to which a positive-side input voltage ViP is applied, and an NMOS transistor Q4, which is always turned on, is connected to an input terminal INP of a differential amplifier circuit 2. A serial circuit having the same impedance as that serial circuit and composed of a capacitor C3, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q9 is also connected to the input terminal INP. A serial circuit composed of a capacitor C2, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q5, which is always turned on, is connected to the other input terminal INM of a differential amplifier circuit 2.