Abstract: A manufacturing method of a semiconductor package includes the following steps. A redistribution structure is formed. An encapsulated semiconductor device is provided on a first side of the redistribution structure, wherein the encapsulated semiconductor device comprising a semiconductor device encapsulated by an encapsulating material. A substrate is bonded to a second side of the redistribution structure opposite to the first side. The redistribution structure includes a plurality of vias connected to one another through a plurality of conductive lines and a redistribution line connected to the plurality of vias, and, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines.

Abstract: A manufacturing method of a semiconductor package includes the following steps. A first semiconductor device is provided over a substrate, wherein the first semiconductor device is offset toward an edge of the substrate. A ring structure is attached to the substrate by a first adhesive layer, wherein the ring structure surrounds the first semiconductor device and comprises an overhang portion cantilevered over the edge of the substrate. A lid structure is attached to the ring structure by a second adhesive layer, wherein the lid structure covers the first semiconductor device and comprises an extending portion covering the overhang portion.

Abstract: A semiconductor die package is provided, including a package substrate, and two semiconductor dies disposed over the package substrate and arranged in a first direction. A ring structure is disposed over the package substrate and surrounds the semiconductor dies. The ring structure includes a first part having a first height and a second part recessed from the bottom surface and having a second height lower than the first height. The first part includes multiple higher parts arranged side by side in at least some of side areas of the ring structure, and the second part includes multiple lower parts between the higher parts. The lower parts include multiple first lower parts arranged in multiple corner areas of the ring structure and multiple second lower parts arranged in opposite side areas of the ring structure extending in the first direction.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

Abstract: Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.

Abstract: A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.

Abstract: A semiconductor die package is provided. The semiconductor die package includes a package substrate, and a first semiconductor die and a second semiconductor die disposed thereon. A ring structure is attached to the package substrate and surrounds the semiconductor dies. A lid structure is attached to the ring structure and disposed over the semiconductor dies, and has an opening exposing the second semiconductor die. A heat sink is disposed over the lid structure and has a portion extending into the opening of the lid structure. A first thermal interface material (TIM) layer is interposed between the lid structure and the first semiconductor die. A second TIM layer is interposed between the extending portion of the heat sink and the second semiconductor die. The first TIM layer has a thermal conductivity higher than the thermal conductivity of the second TIM layer.

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate and a semiconductor device disposed over the package substrate. A ring structure is disposed over the package substrate and laterally surrounds the semiconductor device. The ring structure includes a lower ring portion arranged around the periphery of the package substrate. Multiple notches are formed along the outer periphery of the lower ring portion. The ring structure also includes an upper ring portion integrally formed on the lower ring portion. The upper ring portion laterally extends toward the semiconductor device, so that the inner periphery of the upper ring portion is closer to the semiconductor device than the inner periphery of the lower ring portion. An adhesive layer is interposed between the lower ring portion and the package substrate.

Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Abstract: A semiconductor device includes a first semiconductor die, a second semiconductor die and a package lid. The package lid is disposed over the first semiconductor die and the second semiconductor die. The package lid includes a roof and an island. The roof extends along a first direction and a second direction perpendicular to the first direction and includes a first portion and a second portion. The island protrudes from the first portion of the roof, wherein the island covers and is thermally connected to the first semiconductor die, and the second portion of the roof covers and is physically separated from the second semiconductor die.

Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

Abstract: A package structure is provided. The package structure includes a chip structure having opposite surfaces with different widths. The chip structure has an inclined sidewall between the opposite surfaces. The package structure also includes a protective layer laterally surrounding the chip structure.

Abstract: A semiconductor device package is provided, including a substrate, a semiconductor device, a ring structure, a lid structure, and at least one adhesive member. The semiconductor device is disposed over the substrate. The ring structure is disposed over the substrate and surrounds the semiconductor device. The ring structure comprises a first ring part and a second ring part on opposite sides of the semiconductor device. A first gap is formed between the first ring part and the semiconductor device, a second gap is formed between the second ring part and the semiconductor device, and the first gap is smaller than the second gap. The lid structure is disposed over the ring structure and extends across the semiconductor device. The adhesive member is disposed in the first gap and configured to connect the lid structure and the first surface of the substrate.

Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate. The ring structure surrounds the first chip structure. The top plate covers the ring structure and the first chip structure. The first chip structure has a first sidewall and a second sidewall opposite to the first sidewall, a first distance between the first sidewall and the ring structure is less than a second distance between the second sidewall and the ring structure, the top plate has a first opening, the first opening has a first inner wall and a second inner wall facing each other.

Abstract: A manufacturing method of a semiconductor package includes the following steps. A redistribution structure is formed. An encapsulated semiconductor device is provided on a first side of the redistribution structure, wherein the encapsulated semiconductor device comprising a semiconductor device encapsulated by an encapsulating material. A substrate is bonded to a second side of the redistribution structure opposite to the first side. The redistribution structure includes a plurality of vias connected to one another through a plurality of conductive lines and a redistribution line connected to the plurality of vias, and, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines.

Abstract: A method for forming a semiconductor die package is provided, including disposing a first semiconductor die and a second semiconductor die over an interposer substrate, forming an underfill element over the interposer substrate to surround the first and second semiconductor dies, wherein a portion of the underfill element is between the semiconductor dies, stacking the interposer substrate over a package substrate, and installing a ring structure on the package substrate through an adhesive layer to surround the semiconductor dies. The ring structure has recessed parts recessed from its bottom surface. The recessed parts include first recessed parts arranged in at least one corner area of the ring structure and two second recessed parts arranged in two opposite side areas of the ring structure. The portion of the underfill element between the first and the second semiconductor dies is disposed between the two second recessed parts.

Abstract: A semiconductor package structure includes a first bottom electrical connector, an interposer over the first bottom electrical connector, and a first top electrical connector over the first top via structures. The interposer includes first bottom via structures in contact with the first bottom electrical connector. The interposer also includes a first trace of a first redistribution layer structure over the first bottom via structures. The interposer also includes first via structures over the first redistribution layer. The interposer also includes a first trace of a second redistribution layer structure over the first via structures. The interposer also includes second via structures over the second redistribution layer structure. The first bottom via structures, the first via structures, and the second via structures are separated from each other in a top view.

Abstract: A semiconductor package includes a substrate, a first semiconductor device disposed over the substrate in an offset position toward an edge of the substrate, and a ring structure disposed over the substrate and surrounding the first semiconductor device. The ring structure includes an overhang portion cantilevered over the edge of the substrate.

Abstract: Some embodiments relate to a semiconductor structure including a substrate with conductive pads and conductive bumps disposed on the conductive pads, respectively. A multi-tiered solder-resist structure includes a first tier and a second tier. The first tier includes a first dielectric material and first conductive bump openings defined by inner sidewalls of the first tier. The first tier has a first width measured through the first dielectric material between the inner sidewalls of the first tier in a cross-sectional view. The second tier overlies the first tier and includes a second dielectric material and second conductive bump openings defined by inner sidewalls of the second tier. The second tier has a second width measured through the second dielectric material between the inner sidewalls of the second tier in the cross-sectional view. A ratio of the first width to the second width ranges from 1.1:1 to 2:1.