Abstract: A semiconductor package includes a substrate, a first semiconductor device disposed over the substrate in an offset position toward an edge of the substrate, and a ring structure disposed over the substrate and surrounding the first semiconductor device. The ring structure includes an overhang portion cantilevered over the edge of the substrate.

Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, a semiconductor device, a ring structure, a lid structure, and an adhesive member. The semiconductor device is disposed over the substrate. The ring structure is disposed over the substrate and surrounds the semiconductor device. The lid structure is disposed over the ring structure and extends across the semiconductor device. The adhesive member is disposed in a gap between the ring structure and the semiconductor device and attached to the lid structure and the substrate.

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first tier, a second tier, and a third tier. The first tier includes an interposer. The second tier is disposed on the first tier and includes a bottom die. The third tier is disposed on the second tier and includes a plurality of first dies and at least one second die. The at least one second die is disposed between the plurality of first dies. The plurality of first dies are electrically connected to the bottom die by a plurality of first connectors to form a signal path, the plurality of first dies are electrically connected to the interposer by a plurality of second connectors to form a power path, and the plurality of first connectors are closer to the at least one second die than the plurality of second connectors.

Abstract: In an embodiment, a three-dimensional integrated circuit (3DIC) package includes an interposer, a plurality of connection pads, a plurality of dummy patterns, a plurality of integrated circuit structures and an underfill layer. The connection pads are disposed on and electrically connected to a first side of the interposer. The dummy patterns are disposed on the first side of the interposer and around the plurality of connection pads. The integrated circuit structures are electrically connected to the connection pads through a plurality of first bumps. The underfill layer surrounds the first bumps and covers the dummy patterns.

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a recess in a circuit substrate, and the recess has a first sidewall and a second sidewall. The second sidewall is between the first sidewall and a bottommost surface of the circuit substrate, and the second sidewall is steeper than the first sidewall. The method also includes forming a die package, and the die package has a semiconductor die. The method further includes bonding the die package to the circuit substrate through bonding structures such that a portion of the semiconductor die enters the recess of the circuit substrate. In addition, the method includes forming an underfill material to surround the bonding structures and to fill the recess.

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate and a semiconductor device disposed over the package substrate. A ring structure is disposed over the package substrate and laterally surrounds the semiconductor device. The ring structure includes a lower ring portion arranged around the periphery of the package substrate. Multiple notches are formed along the outer periphery of the lower ring portion. The ring structure also includes an upper ring portion integrally formed on the lower ring portion. The upper ring portion laterally extends toward the semiconductor device, so that the inner periphery of the upper ring portion is closer to the semiconductor device than the inner periphery of the lower ring portion. An adhesive layer is interposed between the lower ring portion and the package substrate.

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a package substrate, a first die, and a stiffener ring. The first die is disposed on the package substrate and has a first sidewall and a second sidewall opposite to each other. The stiffener ring is disposed on the package substrate to surround the first die. The stiffener ring has an inner sidewall facing the first die, and the inner sidewall at least has a slant sidewall facing the first sidewall of the first die.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate. The ring structure surrounds the first chip structure. The top plate covers the ring structure and the first chip structure. The first chip structure has a first sidewall and a second sidewall opposite to the first sidewall, a first distance between the first sidewall and the ring structure is less than a second distance between the second sidewall and the ring structure, the top plate has a first opening, the first opening has a first inner wall and a second inner wall facing each other.

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, two semiconductor dies over the interposer substrate, and an underfill element formed over the interposer substrate and surrounding the semiconductor dies. A ring structure is disposed over the package substrate and surrounds the semiconductor dies. Recessed parts are recessed from the bottom surface of the ring structure. The recessed parts include multiple first recessed parts arranged in each corner area of the ring structure and two second recessed parts arranged in opposite side areas of the ring structure and aligned with a portion of the underfill element between the semiconductor dies. An adhesive layer is interposed between the bottom surface of the ring structure and the package substrate.

Abstract: A package structure is provided. The package structure includes a first package component and a second package component. The second package component includes a substrate and an electronic component disposed on the substrate, and the first package component is mounted to the substrate. The package structure further includes a ring structure disposed on the second package component and around the first package component. The ring structure has a first foot and a second foot, the first foot and the second foot extend toward the substrate, the electronic component is covered by the ring structure and located between the first foot and the second foot, and the first package component is exposed from the ring structure.

Abstract: A semiconductor package includes an encapsulated semiconductor device and a redistribution structure. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulating material. The redistribution structure overlays the encapsulated semiconductor device and includes a plurality of vias and a redistribution line. The plurality of vias are located on different layers of the redistribution structure respectively and connected to one another through a plurality of conductive lines, wherein, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines. The redistribution line is disposed under the plurality of conductive lines and connects corresponding one of the plurality of vias and electrically connected to the semiconductor device through the plurality of vias.

Abstract: A semiconductor package including a lid having one or more heat pipes located on and/or within the lid to provide improved thermal management. A lid for a semiconductor package having one or more heat pipes thermally integrated with the lid may provide more uniform heat loss from the semiconductor package, reduce the risk of damage to the package due to excessive heat accumulation, and may enable the lid to be fabricated using less expensive materials, thereby reducing the costs of a semiconductor package.

Abstract: A semiconductor package includes an interposer, a semiconductor die, an underfill layer and an encapsulant. The semiconductor die is disposed over and electrically connected with the interposer, wherein the semiconductor die has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the first side surface and the second side surface are connected with the front surface and the back surface, and the semiconductor die comprises a chamfered corner connected with the back surface, the first side surface and the second side surface, the chamfered corner comprises at least one side surface. The underfill layer is disposed between the front surface of the semiconductor die and the interposer. The encapsulant laterally encapsulates the semiconductor die and the underfill layer, wherein the encapsulant is in contact with the chamfered corner of the semiconductor die.

Abstract: A method includes forming an interconnect component including a plurality of dielectric layers that include an organic dielectric material, and a plurality of redistribution lines extending into the plurality of dielectric layers. The method further includes bonding a first package component and a second package component to the interconnect component, encapsulating the first package component and the second package component in an encapsulant, and precutting the interconnect component using a blade to form a trench. The trench penetrates through the interconnect component, and partially extends into the encapsulant. The method further includes performing a singulation process to separate the first package component and the second package component into a first package and a second package, respectively.

Abstract: Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

Abstract: A semiconductor structure includes a fan-out package, a packaging substrate, an solder material portions bonded to the fan-out package and the packaging substrate, an underfill material portion laterally surrounding the solder material portions, and at least one cushioning film located on the packaging substrate and contacting the underfill material portion and having a Young's modulus is lower than a Young's modulus of the underfill material portion.

Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

Abstract: A package assembly includes a package substrate, a package lid located on the package substrate and including a plate portion, an outer foot extending from the plate portion, and an inner foot having a height greater than or equal to a height of the outer foot, extending from the plate portion and including a first inner foot corner portion located inside a first corner of the outer foot, and an adhesive that adheres the outer foot to the package substrate and adheres the inner foot to the package substrate.