Abstract: This invention is directed to offer a MOS transistor that has a high source-drain breakdown BVds, a low on resistance and a high electric current driving capacity. On resistance is lowered by forming an N well layer for lowering on resistance in the drift region. The N well layer is disposed beneath the gate electrode and away from the N well layer with a certain space between them. This space ensures the withstand voltage at the edge of the gate electrode of the drain layer side. Also, the N well layer is formed on the surface of an epitaxial layer in the region that includes a P+L layer. The edge of the N well layer of the drain layer side is located near the edge of the P+L layer of the drain layer side and away from the N well layer. This space makes the expansion of depletion layer from the P+L layer easier, further improving the withstand voltage.

Abstract: It is desirable to reduce chip area, lower on resistance and improve electric current driving capacity of a DMOS transistor in a semiconductor device with a DMOS transistor. On the surface of an N type epitaxial layer, a P+W layer of the opposite conductivity type (P type) is disposed and a DMOS transistor is formed in the P+W layer. The epitaxial layer and a drain region are insulated by the P+W layer. Therefore, it is possible to form both the DMOS transistor and other device element in a single confined region surrounded by an isolation layer. An N type FN layer is disposed on the surface region of the P+W layer beneath the gate electrode. An N+D layer, which is adjacent to the edge of the gate electrode of the drain layer side, is also formed. P type impurity layers (a P+D layer and a FP layer), which are located below the drain layer, are disposed beneath the contact region of the drain layer.

Abstract: A magnetic tape cartridge includes a reel around which a magnetic tape is wound, a cartridge casing accommodating the reel rotatably, a reel locking member, a biasing member, a spider, and a lubricant. The reel locking member includes a convex sliding portion and engages with the reel to block a rotation thereof. The biasing member biases the reel locking member so that the reel locking member engages with the reel. The spider includes a supporting surface that comes into contact with the sliding portion and has a concave portion concaved at substantially the center thereof, and a wall portion that surrounds the supporting surface, the spider pushing and moving the reel locking member against a bias force of the biasing member to release the engagement between the reel locking member and the reel. The lubricant is applied between the sliding portion and the supporting surface.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.

Abstract: A magnetic tape cartridge includes a cartridge case, a pair of cylindrical hubs rotatably provided in the cartridge case, and a magnetic tape laid between the hubs and wound around outer peripheries of the hubs. Each of the hubs has an inner diameter portion provided with a height-position determining member. The height-position determining member determines a height position of the hub in the magnetic tape cartridge by contacting a driving shaft inserted in the hub when the magnetic tape cartridge is mounted in a magnetic recording and reproducing apparatus.

Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.

Abstract: There is a problem that a reverse off-leak current becomes too large in a Schottky barrier diode. A semiconductor device of the present invention includes P-type first and second anode diffusion layers formed in an N-type epitaxial layer, N-type cathode diffusion layers formed in the epitaxial layer, a P-type third anode diffusion layer formed in the epitaxial layer so as to surround the first and second anode diffusion layers and to extend toward the cathode diffusion layers, and a Schottky barrier metal layer formed on the first and second anode diffusion layers.

Abstract: In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the present invention, for example, a MOS transistor, a P type diffusion layer 5 as the back gate region, and an N type diffusion layer 8 as a drain region, are formed in an N type epitaxial layer 4. In the P type diffusion layer 5, an N type diffusion layer 7 as a source region and a P type diffusion layer 6 are formed. The P type diffusion layer 6 is formed by performing ion implantation twice so as to correspond to a shape of a contact hole 15. Moreover, impurity concentrations in surface and deep portions of the P type diffusion layer 6 are controlled. By use of this structure, a device size is reduced, and an operation of a parasitic NPN transistor is suppressed.

Abstract: There is a problem that a reverse off-leak current becomes too large in a Schottky barrier diode. A semiconductor device of the present invention includes a P-type first anode diffusion layer formed in an N-type epitaxial layer, a second anode diffusion layer which is formed so as to surround the first anode diffusion layer, and which has an impurity concentration lower than that of the first anode diffusion layer, N-type cathode diffusion layers formed in the epitaxial layer, and a Schottky barrier metal layer formed on the first and second anode diffusion layers.

Abstract: A tape cartridge is configured to include a cartridge case, a hub, around which a magnetic tape is wound around and is housed in the cartridge case rotatably, and a drive apparatus for driving the hub to rotate, the drive apparatus being arranged between a bottom portion of the hub and the cartridge case.

Abstract: The invention is directed to providing an electrostatic breakdown protection circuit having an enhanced performance of protecting an internal circuit from a surge voltage such as static electricity (an operation speed or resistance to electrostatic breakdown). An N-channel type MOS transistor is connected between a wiring and a VSS (ground voltage) wiring. A first capacitor is connected between the wiring and a gate of the MOS transistor, and a second capacitor is connected between the VSS wiring and the gate. A voltage applied to an input/output terminal is divided by these capacitors, and the divided voltage is applied to the gate. When a surge voltage occurs, the MOS transistor is forced to turn on by the divided voltage to flow a current, thereby protecting an internal circuit. When a larger surge voltage occurs, a parasitic bipolar transistor turns on. A Zener diode is disposed between the gate and the VSS wiring in order to prevent a voltage applied to the gate from exceeding a predetermined voltage.

Abstract: A tape cartridge that has a clamp force to a block body and that secures a leader tape to a leader block is provided. Nail portions (63a, 64a) formed on the outer surface sides of a pair of leg portions (63, 64) of a clamper (36?) are secured to securing grooves (53, 54) formed on side walls of a assembling concave portion (50) of a block body (40) to secure the block body (40) and the clamper (36?). At this point, with concave grooves (73, 74) and a reinforcement rib (75) formed on an inner surface side of a base portion (60) that composes the clamper (36?) in the elongation direction of the leg portions 63 and 64. Thus, when the clamper (36?) is pushed, it can be prevented from being damaged and a desired clamp force can be obtained.

Abstract: A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is formed in the first low concentration drain region so that the second low concentration drain region is very close to the outer boundary of the second low concentration drain region and has at least a higher impurity concentration than the first low concentration drain region. A high concentration (N+ type) source region is formed adjacent to the other end of said gate electrode, and a high concentration (N+ type) drain region is formed in the second low concentration drain region having the designated space from one end of the gate electrode.

Abstract: In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.

Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.

Abstract: In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across an upper surface of the N-type buried diffusion layer over a wide range to form a PN junction region for an overvoltage protection. A P-type diffusion region is formed so as to be connected to the P-type buried diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. This structure makes it possible to prevent a concentration of a breakdown current and protect the semiconductor device from an overvoltage.

Abstract: The invention provides a high voltage MOS transistor having a high source/drain breakdown voltage of about 300V and a low on-resistance. An N-type body layer is formed extending from a source layer side to under a gate electrode. A P-type second drift layer is formed in an epitaxial semiconductor layer by being diffused deeper than a first drift layer, extending from under the first drift layer to under the gate electrode and forming a PN junction with the body layer under the gate electrode. A surface of the body layer between this second drift layer and the source layer serves as a channel region. The first drift layer is formed at a distance from a left end of the gate electrode where electric field concentration easily occurs.

Abstract: The invention provides a high voltage MOS transistor having a high gate breakdown voltage and a high source/drain breakdown voltage and having a low on-resistance. A gate electrode is formed on an epitaxial silicon layer with a LOCOS film being interposed therebetween. A P-type first drift layer is formed on the left side of the LOCOS film, and a P+-type source layer is disposed on the surface of the epitaxial silicon layer on the right side of the LOCOS film, being opposed to the first drift layer over the gate electrode. A P-type second drift layer is formed by being diffused in the epitaxial silicon layer deeper than the first drift layer, extending from under the first drift layer to under the left side of the LOCOS film. A recess is formed in a bottom portion of the second drift layer under the left end of the LOCOS film.

Abstract: A recording medium cartridge comprises an information recording medium, an inner rotor, and a pair of shutter members that are piled and accommodated in a cartridge casing. When the inner rotor is rotated, the opening part of the cartridge casing is opened and closed by the shutter members. On the overlapping surface of the shutter and the inner rotor, a plurality of ribs for reducing the contact area of the shutter and the inner rotor are provided. Further, in side parts of the shutter members, first overlapped parts and second overlapped parts are respectively provided through first step parts and second step parts in the moving directions of the shutter members. When the side parts are overlapped on each other, the first overlapped part of one shutter member and the first overlapped part of the other shutter member are continuously connected together through the first step parts on the upper surface side of the shutter members.

Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.