Patents by Inventor Shuichi Kikuchi

Shuichi Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070145529
    Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, recombination of free carriers (positive holes) on the surface is prevented. Thus, a desired hfe value can be realized.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 28, 2007
    Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
  • Publication number: 20070148892
    Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, even in a case where the collector region is narrowed, a desired hfe value can be realized. Thus, the device size can be reduced.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 28, 2007
    Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
  • Patent number: 7217612
    Abstract: A semiconductor device including: a first gate insulating film which is pattern-formed on an N type well region within a P type semiconductor substrate; a second gate insulating film which is formed on the semiconductor substrate except for this first gate insulating film; a gate electrode, which is formed in such a manner that this gate electrode is bridged over the first gate insulating film and the second gate insulating film; a P type body region which is formed in such a manner that this P type body region is located adjacent to the gate electrode; an N type source region and a channel region, which are formed within this P type body region; and an N type drain region which is formed at a position separated from the P type body region.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: May 15, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Eiji Nishibe, Shuichi Kikuchi
  • Publication number: 20070096261
    Abstract: In a conventional semiconductor device, there is a problem that zener diode characteristics vary due to a crystal defect on a silicon surface, and the like. In a semiconductor device of the present invention, an N type epitaxial layer 4 is formed on a P type single crystal silicon substrate 2. In the epitaxial layer 4, P type diffusion layers 5, 6, 7 and 8 as anode regions and an N type diffusion layer 9 as a cathode region are formed. A PN junction region between the P type diffusion layer 8 and the N type diffusion layer 9 forms a zener diode 1. By use of this structure, a current path is located in a deep portion of the epitaxial layer 4. Thus, it is made possible to prevent a variation in a saturation voltage of the zener diode 1 due to a crystal defect on a surface of the epitaxial layer 4, and the like.
    Type: Application
    Filed: August 29, 2006
    Publication date: May 3, 2007
    Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
  • Publication number: 20070075363
    Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.
    Type: Application
    Filed: September 26, 2006
    Publication date: April 5, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Seiji Otake, Ryo Kanda, Shuichi Kikuchi
  • Publication number: 20070063274
    Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.
    Type: Application
    Filed: February 22, 2006
    Publication date: March 22, 2007
    Inventors: Ryo Kanda, Shuichi Kikuchi, Seiji Otake, Hirotsugu Hata
  • Publication number: 20070057321
    Abstract: In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.
    Type: Application
    Filed: September 7, 2006
    Publication date: March 15, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shuichi Kikuchi, Kiyofumi Nakaya, Shigeaki Okawa
  • Patent number: 7161210
    Abstract: A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: January 9, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Eiji Nishibe, Shuichi Kikuchi, Takuya Suzuki
  • Publication number: 20060244091
    Abstract: In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, P-type diffusion layers are formed in a floating state closer to a cathode region side than the P-type diffusion layer, and are capacitively coupled with a metal layer to which an anode potential is applied. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.
    Type: Application
    Filed: March 30, 2006
    Publication date: November 2, 2006
    Inventors: Shuichi Kikuchi, Shigeaki Okawa, Kiyofumi Nakaya, Toshiyuki Takahashi
  • Publication number: 20060242385
    Abstract: Disclosed is a technology of generating an instruction set architecture (hereinafter, referred to as ‘ISA’) and a series of logic circuit configuration information of a processor for executing an application program from an application program described in a high-level language. The present invention also relates to a custom LSI development platform technology which can design, develop, and manufacture the application specific custom LSI in a short time by applying the generated ISA and logic circuit configuration information to a dynamic logic circuit reconfigurable processor. Furthermore, disclosed is a dynamically reconfigurable processor, which is reconfigurable using the generated logic circuit configuration information. Associated methods are also disclosed.
    Type: Application
    Filed: November 4, 2005
    Publication date: October 26, 2006
    Inventors: Kazuaki Murakami, Makoto Shuto, Lovic Gauthier, Takuma Matsuo, Tetsuya Hasebe, Shuichi Kikuchi
  • Publication number: 20060237566
    Abstract: A tape cartridge that has a clamp force to a block body and that secures a leader tape to a leader block is provided. Nail portions (63a, 64a) formed on the outer surface sides of a pair of leg portions (63, 64) of a damper (36?) are secured to securing grooves (53, 54) formed on side walls of a assembling concave portion (50) of a block body (40) to secure the block body (40) and the damper (36?). At this point, with concave grooves (73, 74) and a reinforcement rib (75) formed on an inner surface side of a base portion (60) that composes the damper (36?) in the elongation direction of the leg portions 63 and 64. Thus, when the damper (36?) is pushed, it can be prevented from being damaged and a desired clamp force can be obtained.
    Type: Application
    Filed: January 8, 2004
    Publication date: October 26, 2006
    Applicant: Sony Corporation
    Inventors: Hitomi Chiba, Shuichi Kikuchi, Kazuo Sasaki, Takaaki Sanpei, Mitsue Sakurai
  • Patent number: 7127732
    Abstract: The present invention is related to a disc cartridge in which an optical disc, an inner shell and shutter members are housed in a main cartridge body unit, formed by abutting and combining upper and lower shells and in which the inner shell is run in rotation to cause the shutter members to open or close an aperture provided in the main cartridge body unit. The inner shell is formed by a resin molding portion comprised of a first molded portion for forming the inner shell and a second molded portion connected to the first molded portion. The second molded portion is provided at a position forming the aperture in the inner shell and is connected to the first molded portion through a flanged thin-walled section. The inner shell is formed by severing the second molded portion and the flanged thin-walled section.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: October 24, 2006
    Assignee: Sony Corporation
    Inventors: Yuji Iwaki, Shuichi Kikuchi, Teiko Hoshi, Naoki Inoue, Manabu Obata, Mitsuyoshi Kawaguchi
  • Patent number: 7118061
    Abstract: A tape reel in which molding quality of a flange unit is improved so as to improve reliability at the time when a magnetic tape runs at high speed, and a tape cartridge having the same. A plurality of reference planes (152v) formed between a chucking gear (152b) and an outer peripheral rib (152r2) formed at an outer peripheral side of this chucking gear (152b) are provided separately from the outer peripheral rib (152r2). And the reference plane (152v) is formed with edge planes of each of a first rib (152v1) extending toward a circumference and a second rib (152v2) extending toward a direction crossing the first rib (152v1). According to this arrangement, a volume at a portion constituting the reference plane (152v) is made smaller, occurrence of a sink after a resin is hardened is suppressed, and molding quality of the flange unit (152) is improved so that straight runnability of the magnetic tape at high speed running and reliability in recording/reproducing operation are improved.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: October 10, 2006
    Assignee: Sony Corporation
    Inventors: Takaaki Sanpei, Shuichi Kikuchi, Kazuo Sasaki, Mitsue Sakurai, Hitomi Chiba
  • Publication number: 20060220125
    Abstract: In a semiconductor device of the present invention, a thin gate oxide film is formed on a P-type diffusion layer. On the gate oxide film, a gate electrode is formed. N-type diffusion layers are formed in the P-type diffusion layer, and the N-type diffusion layer is used as a drain region. The N-type diffusion layer is diffused in a ? shape at least below the gate electrode. With the structure described above, a diffusion region of the N-type diffusion layer expands and comes to be a low-concentration region in the vicinity of a surface of an epitaxial layer. Thus, it is possible to reduce an electric field from the gate electrode and an electric field between a source and a drain.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 5, 2006
    Inventors: Seiji Otake, Shuichi Kikuchi
  • Publication number: 20060223259
    Abstract: Disclosed is that in a method of manufacturing a semiconductor device of the present invention, when first and second P type diffusion layers using as a backgate region, these layers are formed in such a way that their impurity concentration peaks are shifted, respectively. Then, in the backgate region, a concentration profile of a region where an N type diffusion layer is formed is gradually established. After that, impurity ions, which form the N type diffusion layer, are implanted, and thereafter a thermal treatment is performed to diffuse the N type diffusion layer in a y shape at a lower portion of a gate electrode. This manufacturing method makes it possible to implement an electric filed relaxation in a drain region.
    Type: Application
    Filed: March 28, 2006
    Publication date: October 5, 2006
    Inventors: Seiji Otake, Shuichi Kikuchi
  • Publication number: 20060220099
    Abstract: In a conventional semiconductor device, there has been a problem that, in a region where a wiring layer to which a high electric potential is applied traverses a top surface of an isolation region, the withstand voltage is deteriorated. In a semiconductor device of the present invention, an epitaxial layer is deposited on a substrate, and an LDMOSFET is formed in one region divided by an isolation region. In a region where a wiring layer connected to a drain electrode traverses a top surface of the isolation region, a conductive plate having a ground electric potential and another conductive plate in a floating state are formed under the wiring layer. With this structure, electric field is reduced in the vicinity of the isolation region under the wiring layer, whereby a withstand voltage of the LDMOSFET is increased.
    Type: Application
    Filed: March 27, 2006
    Publication date: October 5, 2006
    Inventors: Shuichi Kikuchi, Shigeaki Okawa, Kiyofumi Nakaya, Toshiyuki Takahashi
  • Publication number: 20060220166
    Abstract: In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, a P-type diffusion layer is formed to be connected to a P-type diffusion layer and is extended to a cathode region. A metal layer to which an anode electrode is applied is formed above the P-type diffusion layer, thereby making it possible to obtain a field plate effect. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Inventors: Shuichi Kikuchi, Shigeaki Okawa, Kiyofumi Nakaya, Toshiyuki Takahashi
  • Patent number: 7103902
    Abstract: A recording medium cartridge includes a disc, an inner rotor and a shutter in a shell. Torque is applied to the inner rotor by a coil spring to drive the shutter so as to maintain the closed state of an opening part provided in the shell. When the recording medium cartridge is inserted into a disc device, the inner rotor is rotated against the resilient force of the coil spring by a shutter opening mechanism provided in the disc recording and reproducing device. Thus, the shutter is moved to a position where the opening part provided in the shell is opened. When the cartridge is ejected from the disc device, the inner rotor is rotated by the resilient force of the coil spring to close the shutter.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: September 5, 2006
    Assignee: Sony Corporation
    Inventors: Yasuyuki Abe, Shuichi Kikuchi, Susumu Shibagaki
  • Patent number: 7103898
    Abstract: A method for producing an inner shell used for a disc cartridge in which an optical disc, an inner shell and shutter members are housed in a main cartridge body unit. The inner shell provided in the main cartridge body unit includes a first molded portion, provided with an aperture, a second molded portion having a resin injection port and molded at a position where the aperture is formed, and a flanged thin-walled section connecting the first and second molded portions to each other. The method includes the steps of injecting molten resin into a cavity defined by a fixed metal die and a movable metal die for molding the first molded portion, the second molded portion, and the flanged thin-walled section, and severing the flanged thin-walled section by a punch provided to the movable metal die before the molten resin injected into the cavity is cooled and solidified.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: September 5, 2006
    Assignee: Sony Corporation
    Inventors: Yuji Iwaki, Shuichi Kikuchi, Teiko Hoshi, Naoki Inoue, Manabu Obata, Mitsuyoshi Kawaguchi
  • Patent number: 7103900
    Abstract: The present invention is relative to a disc cartridge in which an optical disc (3), an inner shell (4) and shutter members (5a), (5b) are housed in a main cartridge body unit (2), formed by abutting and combining upper and lower shells (6), (7), and in which the inner shell is run in rotation to cause the shutter members (5a), (5b) to open or close an aperture (24) provided in the main cartridge body unit (2). On an inner side of the peripheral wall sections of the upper and lower shells, abutted to each other, a crank-shaped dust intrusion prohibiting unit (21A) is provided for prohibiting intrusion of dust and dirt from the abutting surfaces of the peripheral wall sections of the upper and lower shells towards the optical disc housed in the main cartridge body unit to protect the optical disc housed in the main cartridge body unit.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: September 5, 2006
    Assignee: Sony Corporation
    Inventors: Yuji Iwaki, Shuichi Kikuchi, Teiko Hoshi, Naoki Inoue, Manabu Obata, Mitsuyoshi Kawaguchi