Patents by Inventor Shuichi Kikuchi

Shuichi Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040051125
    Abstract: To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed on an N-type well region formed in a P-type semiconductor substrate to a selective oxide film, a P-type source region formed so that the source region is adjacent to the gate electrode, a P-type drain region formed in a position apart from the gate electrode and a P-type drift region (an LP layer) formed so that the drift region surrounds the drain region, and is characterized in that a P-type impurities layer (an FP layer) is formed so that the impurities layer is adjacent to the drain region.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 18, 2004
    Applicant: Sanyo Electric Co., Ltd., a Osaka, Japan corporation
    Inventors: Shuichi Kikuchi, Eiji Nishibe
  • Patent number: 6696734
    Abstract: A semiconductor device has a gate electrode formed on P type semiconductor substrate through a gate insulation film, a low concentration N− type drain region formed so as to be adjacent to the gate electrode, a high concentration N+ type drain region separated from the other end of said gate electrode and included in said low N− type drain region, and a middle concentration N type layer having high impurity concentration peak at a position of the predetermined depth in said substrate at a region spanning at least from said gate electrode to said high concentration N+ type drain region, and formed so that high impurity concentration becomes low at a region near surface of the substrate.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: February 24, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Eiji Nishibe, Takuya Suzuki
  • Publication number: 20040028299
    Abstract: A bearing unit is provided which includes a shaft (51) to support rotatably, radial bearing (55) to support the shaft (51) circumferentially, a thrust bearing (66) to support the shaft (51) in the direction of thrusting, and a housing (56) having the radial bearing (55) and thrust bearing (66) disposed therein and in which a viscous fluid (57) is filled. The housing (56) has a sealed structure except for a shaft insertion hole (65) formed therein and through which the shaft 51 is introduced. Between the outer surface of the shaft (51) and the inner surface of the shaft insertion hole (65), there is defined a gap (69) having a sufficient width to prevent the viscous fluid (57) filled in the housing (56) from leaking out of the latter. The housing (56) is formed as a one-piece structure by molding a synthetic resin.
    Type: Application
    Filed: May 15, 2003
    Publication date: February 12, 2004
    Inventors: Yuji Shishido, Kenichiro Yazawa, Shinichiro Kato, Shuichi Kikuchi, Toru Ujiie
  • Patent number: 6669023
    Abstract: A storage case is comprised of a case main body, a cover, a rotating means and a tilt means. The case main body has a bottom plate, the front plate, a back plate, a right plate and a left plate which are arranged so that the front, back, right and left plates surround four sides of the bottom plate. The cover is installed to the case main body so as to open and close an opening of the case main body. The rotating means swingably and slidably connects the cover with the case main body. The rotating means has a rotation shaft installed to the cover and a bearing portion installed to the case main body. The bearing portion is formed into an elongate groove extending in a vertical direction of the case main body. The front plate is tilted forward by the tilt means.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: December 30, 2003
    Assignee: Sony Corporation
    Inventors: Shuichi Kikuchi, Rie Izu
  • Patent number: 6638827
    Abstract: To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed on an N-type well region formed in a P-type semiconductor substrate to a selective oxide film, a P-type source region formed so that the source region is adjacent to the gate electrode, a P-type drain region formed in a position apart from the gate electrode and a P-type drift region (an LP layer) formed so that the drift region surrounds the drain region, and is characterized in that a P-type impurities layer (an FP layer) is formed so that the impurities layer is adjacent to the drain region.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: October 28, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Eiji Nishibe
  • Publication number: 20030174640
    Abstract: The present invention is relative to a disc cartridge in which an optical disc (3), an inner shell (4) and shutter members (5a), (5b) are housed in a main cartridge body unit (2), formed by abutting and combining upper and lower shells (6), (7), and in which the inner shell is run in rotation to cause the shutter members (5a), (5b) to open or close an aperture (24) provided in the main cartridge body unit (2). On an inner side of the peripheral wall sections of the upper and lower shells, abutted to each other, a crank-shaped dust intrusion prohibiting unit (21A) is provided for prohibiting intrusion of dust and dirt from the abutting surfaces of the peripheral wall sections of the upper and lower shells towards the optical disc housed in the main cartridge body unit to protect the optical disc housed in the main cartridge body unit.
    Type: Application
    Filed: February 27, 2003
    Publication date: September 18, 2003
    Inventors: Yuji Iwaki, Shuichi Kikuchi, Teiko Hoshi, Naoki Inoue, Manabu Obata, Mitsuyoshi Kawaguchi
  • Patent number: 6614622
    Abstract: To provide a new shutter open/close mechanism suitable for use with a cartridge body (6) whose front end is formed in an arbitrary shape for easily knowing a correct direction of insertion in a recorder/player, a guide recess (36) to support a shutter plate (25) movably is formed on a main side of the cartridge body (6) to be oblique relative to the width of the cartridge body (6). The shutter open/close mechanism (26) includes a guide member (31) supporting the shutter plate (25) and movably engaged in the guide recess (36), an operating member (32) to move the guide member (31), a transmission member (33) connecting the guide member (31) and operating member (32) to each other to transmit an operating force from the operating member (32) to the guide member (31), and support surfaces (37) formed on the cartridge body (6) to support the operating member (32) movably. The transmission member (33) is pivotably connected to the guide and operating members (31) and (32).
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 2, 2003
    Assignee: Sony Corporation
    Inventors: Shuichi Kikuchi, Rie Izu
  • Patent number: 6614075
    Abstract: A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: September 2, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yumiko Akaishi, Takuya Suzuki, Shinya Mori, Yuji Tsukada, Yuichi Watanabe, Shuichi Kikuchi
  • Publication number: 20030159409
    Abstract: An engageable pawl member is provided so as to be swingable about a supporting shaft so that a pawl tip is movable along a moving path for a strapping band. The engageable pawl member is pulled forwardly in a swinging direction by a helical tension spring to push the pawl tip against the strapping band. The engageable pawl member shifts forwardly, following the movement of the strapping band in a feeding direction, and the strapping band is sandwiched and held between the engageable paw member and a holding guide. Then, the engageable pawl member follows the movement of the strapping band in a direction to pull back, and the engageable pawl member shifts backwardly so that the pawl tip moves in a direction out of the moving path for the strapping band.
    Type: Application
    Filed: February 25, 2003
    Publication date: August 28, 2003
    Applicant: NICHIRO KOGYO CO., LTD.
    Inventors: Katsumi Oda, Tetsuya Hoshino, Shuichi Kikuchi
  • Patent number: 6608336
    Abstract: To reduce ON-state resistance with desired withstand voltage secured, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP layer (a P-type body region) formed so that the LP layer is adjacent to the gate electrode, an N-type source region and a channel region respectively formed in the LP layer, an N-type drain region formed in a position apart from the LP layer and an LN layer (a drift region) formed so that the LN layer surrounds the drain region is characterized in that a P-type layer ranging to the LP layer is formed under the gate electrode.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: August 19, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Eiji Nishibe
  • Publication number: 20030153154
    Abstract: A manufacturing method of this invention has an ion-implantation process for threshold voltage adjustment of an MOS transistor, including a process to form a first well of an opposite conductivity type in a substrate of one conductivity type, to form a second well of the opposite conductivity type having higher impurity concentration than that in the first well, under a region where a thin gate insulation film is formed, to form gate insulation films on the first well and the second well, each having a different thickness, to ion-implant first impurities of the one conductivity type into the wells of the opposite conductivity type under the condition that the impurities penetrate the gate insulation films of different thicknesses and to ion-implant second impurities of the one conductivity type into the second well of the opposite conductivity type under the condition that the second impurities penetrate the thin gate insulation film but do not penetrate the thick gate insulation film.
    Type: Application
    Filed: November 27, 2002
    Publication date: August 14, 2003
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Masafumi Uehara, Shuichi Kikuchi, Masaaki Momen
  • Patent number: 6599782
    Abstract: To enhance the withstand voltage of an LD MOS transistor, a method of fabricating a semiconductor device according to the invention is characterized in that a process for forming a drift region is composed of a step for implanting phosphorus ions and arsenic ions different in a diffusion coefficient into the superficial layer of a substrate, a step for forming a selective oxide film (a first gate insulating film) 9A and an element isolation film 9B by selective oxidation and diffusing the phosphorus ions and the arsenic ions and a step for implanting and diffusing boron ions, and in that in the step for forming the selective oxide film 9A and the element isolation film 9B by selective oxidation in a state in which an oxide film and a polycrystalline silicon film are laminated on the substrate, only a drift region formation region is selectively oxidized in a state in which the polycrystalline silicon film is removed.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: July 29, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Yumiko Akaishi, Takuya Suzuki
  • Patent number: 6583956
    Abstract: To easily know a correct direction of insertion into a recorder/player and assure a large width of an access opening through which the optical head approaches an optical disc, a disc cartridge is provided which includes an access opening (21) formed in a cartridge body (6) and through which a part of the recording area of an optical disc (5), extending between lead-in and lead-out areas, is exposed outside for data read and write, a pair of shutter members (25), (26) provided movably towards and away from each other to open and close the access opening (21); and a shutter open/close mechanism (27) having a pair of guide recesses (36a) and (36b) formed in a main side the of the cartridge body (6) obliquely in relation to the width of the cartridge body (6) to support the pair of shutter members (25) and (26), respectively, to be movable.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: June 24, 2003
    Assignee: Sony Corporation
    Inventors: Shuichi Kikuchi, Rie Izu
  • Patent number: 6560193
    Abstract: To provide a new shutter open/close mechanism (26) suitable for use with a cartridge body whose front end is formed in an arbitrary shape for easily knowing a correct direction of insertion in a recorder/player, a guide recess (36) to support a shutter plate (25) movably is formed on a main side of the cartridge body (6) to be oblique relative to the width of the cartridge body (6). The shutter open/close mechanism (26) includes a guide member (31) supporting the shutter plate (25) and movably engaged in the guide recess (36), an operating member (32) to move the guide member (31), a transmission member (33) connecting the guide member (31) and operating member (32) to each other to transmit an operating force from the operating member (32) to the guide member (31), and support surfaces (37) formed on the cartridge body (6) to support the operating member (32) movably.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: May 6, 2003
    Assignee: Sony Corporation
    Inventors: Shuichi Kikuchi, Rie Izu
  • Patent number: 6559504
    Abstract: To increase the withstand voltage and reduce ON-state resistance, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP layer (a P-type body region) formed so that the LP layer is adjacent to the gate electrode, an N-type source region and a channel region respectively formed in the LP layer, an N-type drain region formed in a position apart from the LP layer and an LN layer (a drift region) formed so that the LN layer surrounds the drain region is characterized in that the LP layer is formed up to the side of the drain region through an active region under the gate electrode and an SLN layer is formed from the drain region to a part before the active region.
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: May 6, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Eiji Nishibe, Shuichi Kikuchi, Takao Maruyama
  • Publication number: 20030067864
    Abstract: An optical information medium having an ink-accepting layer that may secure a high-gloss printed surface similar to print image quality of print image on photographic paper is provided. The optical disk 1 is constituted by sequentially laminating concavo-convex information pits 3, a recording layer 4, a reflective layer 5, a protective layer 6, a second printing layer 7, and an ink-accepting layer 8 on a transparent substrate 2 made of synthetic resin such as polycarbonate.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 10, 2003
    Inventors: Shuichi Kikuchi, Rie Izu, Mariko Takiue
  • Publication number: 20030030105
    Abstract: A die size is reduced in a semiconductor device which has a gate electrode formed on a first gate insulation film and a second gate insulation film, source and drain regions (N− layers and N+ layers) formed adjacent to the gate electrode and a channel region, wherein at least the gate electrode, the channel region and the source and drain regions are polygonal in shape.
    Type: Application
    Filed: August 9, 2002
    Publication date: February 13, 2003
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Eiji Nishibe, Shuichi Kikuchi, Masaaki Momen
  • Publication number: 20030032266
    Abstract: The semiconductor device of this invention has a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over the three gate insulating films. The ion implantation of the impurity for controlling the threshold voltage is performed only under the thinnest gate insulating film of the three gate insulating films.
    Type: Application
    Filed: August 9, 2002
    Publication date: February 13, 2003
    Inventors: Shuichi Kikuchi, Masaaki Momen
  • Publication number: 20030032223
    Abstract: A transistor of a semiconductor device has an increased driving capacity. The semiconductor device has a first gate insulation film formed by a selective oxidation, a second gate insulation film formed by thermal oxidation and a gate electrode formed across the first and the second gate insulation films. The second gate insulation film is composed of a thicker gate insulation film and a thinner gate insulation film.
    Type: Application
    Filed: August 9, 2002
    Publication date: February 13, 2003
    Inventors: Shuichi Kikuchi, Masaaki Momen
  • Publication number: 20030030115
    Abstract: The semiconductor device of this invention has a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over the three gate insulating films. The ion implantation of the impurity for controlling the threshold voltage is performed only under the thinnest gate insulating film of the three gate insulating films.
    Type: Application
    Filed: August 9, 2002
    Publication date: February 13, 2003
    Inventors: Shuichi Kikuchi, Masaaki Momen