Patents by Inventor Shuichi Kikuchi

Shuichi Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6897525
    Abstract: In order to improve the characteristics of the high breakdown voltage MOS, a semiconductor device of the present invention is characterized in that an LDMOS transistor, which comprises a source region 4, a channel region 8, and a drain region 5, and a gate electrode 7 formed on the channel region 8, and a drift region formed between the channel region 8 and the drain region 5, wherein an N?-type low concentration layer 22 serving as the drift region is formed shallowly at least below the gate electrode 7 (first N?-type layer 22A) but formed deeply in a neighborhood of the drain region 5 (second N?-type layer 22B).
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: May 24, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Yumiko Akaishi
  • Patent number: 6893926
    Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N?-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N?-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: May 17, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Masafumi Uehara, Eiji Nishibe, Katsuyoshi Anzai
  • Patent number: 6885521
    Abstract: A metal shutter for use with a disc cartridge, has a following structure. A screen portion of the shutter is formed on an outside surface thereof with an indication area. The indication area includes a stamped rough surface part which is configured to constitute a given pattern. The screen portion is formed, on an inside surface thereof at a portion corresponding to the indication area, with another stamped rough surface area.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: April 26, 2005
    Assignee: Sony Corporation
    Inventor: Shuichi Kikuchi
  • Publication number: 20050081231
    Abstract: There are provided a cartridge main body, in which a disk insertion/ejection port for housing an optical disk and for inserting and ejecting the optical disk to be housed, is formed on one of side surfaces at an insertion end for an disk drive apparatus, and a disk holding body which holds the optical disk to be housed in the cartridge main body and is movable in an insertion direction into the disk drive apparatus. If the disk holding body moves to the side of the disk insertion/ejection port in the cartridge main body, the disk holding body makes at least a part of the holding optical disk expose to outside of the disk insertion/ejection port.
    Type: Application
    Filed: October 6, 2004
    Publication date: April 14, 2005
    Inventors: Yasuyuki Abe, Shuichi Kikuchi
  • Publication number: 20050061902
    Abstract: A tape reel in which the reliability while running a magnetic tape at high speed is improved and a tape cartridge including the same. By configuring an annular chucking gear (152b) formed in a center section of a bottom surface of a lower flange (152) of a tape reel (150) with a perpendicular wall, idling and floating of the tape reel is suppressed, and thus, the running stability and linearity of the magnetic tape during high-speed rotation of the tape reel (150) are secured, and the reliability of the tape cartridge with regard to high speed operations is improved.
    Type: Application
    Filed: October 31, 2002
    Publication date: March 24, 2005
    Inventors: Takaaki Sanpei, Shuichi Kikuchi, Kazuo Sasaki, Mitsue Sakurai, Toshiya Kurokawa, Katsumi Maekawa, Hitomi Chiba
  • Patent number: 6844593
    Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N?-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N?-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: January 18, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Masafumi Uehara, Eiji Nishibe, Katsuyoshi Anzai
  • Publication number: 20040257705
    Abstract: A recording medium cartridge comprises an information recording medium, an inner rotor, and a pair of shutter members that are piled and accommodated in a cartridge casing. When the inner rotor is rotated, the opening part of the cartridge casing is opened and closed by the shutter members. On the overlapping surface of the shutter and the inner rotor, a plurality of ribs for reducing the contact area of the shutter and the inner rotor are provided. Further, in side parts of the shutter members, first overlapped parts and second overlapped parts are respectively provided through first step parts and second step parts in the moving directions of the shutter members. When the side parts are overlapped on each other, the first overlapped part of one shutter member and the first overlapped part of the other shutter member are continuously connected together through the first step parts on the upper surface side of the shutter members.
    Type: Application
    Filed: June 21, 2004
    Publication date: December 23, 2004
    Inventors: Yasuyuki Abe, Shuichi Kikuchi
  • Publication number: 20040255314
    Abstract: A recording medium cartridge includes a disc, an inner rotor and a shutter in a shell. Torque is applied to the inner rotor by a coil spring to drive the shutter so as to maintain the closed state of an opening part provided in the shell. When the recording medium cartridge is inserted into a disc device, the inner rotor is rotated against the resilient force of the coil spring by a shutter opening mechanism provided in the disc recording and reproducing device. Thus, the shutter is moved to a position where the opening part provided in the shell is opened. When the cartridge is ejected from the disc device, the inner rotor is rotated by the resilient force of the coil spring to close the shutter.
    Type: Application
    Filed: April 28, 2004
    Publication date: December 16, 2004
    Inventors: Yasuyuki Abe, Shuichi Kikuchi, Susumu Shibagaki
  • Patent number: 6815284
    Abstract: A manufacturing method of this invention has an ion-implantation process for threshold voltage adjustment of an MOS transistor, including a process to form a first well of an opposite conductivity type in a substrate of one conductivity type, to form a second well of the opposite conductivity type having higher impurity concentration than that in the first well, under a region where a thin gate insulation film is formed, to form gate insulation films on the first well and the second well, each having a different thickness, to ion-implant first impurities of the one conductivity type into the wells of the opposite conductivity type under the condition that the impurities penetrate the gate insulation films of different thicknesses and to ion-implant second impurities of the one conductivity type into the second well of the opposite conductivity type under the condition that the second impurities penetrate the thin gate insulation film but do not penetrate the thick gate insulation film.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: November 9, 2004
    Assignees: Sanyo Electric Co., Ltd., Niigata Sanyo Electronics Co., Ltd.
    Inventors: Masafumi Uehara, Shuichi Kikuchi, Masaaki Momen
  • Publication number: 20040212033
    Abstract: A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is formed in the first low concentration drain region so that the second low concentration drain region is very close to the outer boundary of the second low concentration drain region and has at least a higher impurity concentration than the first low concentration drain region. A high concentration (N+ type) source region is formed adjacent to the other end of said gate electrode, and a high concentration (N+ type) drain region is formed in the second low concentration drain region having the designated space from one end of the gate electrode.
    Type: Application
    Filed: May 24, 2004
    Publication date: October 28, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Eiji Nishibe
  • Publication number: 20040183145
    Abstract: A transistor of a semiconductor device has an increased driving capacity. The semiconductor device has a first gate insulation film formed by a selective oxidation, a second gate insulation film formed by thermal oxidation and a gate electrode formed across the first and the second gate insulation films. The second gate insulation film is composed of a thicker gate insulation film and a thinner gate insulation film.
    Type: Application
    Filed: April 5, 2004
    Publication date: September 23, 2004
    Inventors: Shuichi Kikuchi, Masaaki Momen
  • Publication number: 20040178459
    Abstract: A semiconductor device including: a first gate insulating film which is pattern-formed on an N type well region within a P type semiconductor substrate; a second gate insulating film which is formed on the semiconductor substrate except for this first gate insulating film; a gate electrode, which is formed in such a manner that this gate electrode is bridged over the first gate insulating film and the second gate insulating film; a P type body region which is formed in such a manner that this P type body region is located adjacent to the gate electrode; an N type source region and a channel region, which are formed within this P type body region; and an N type drain region which is formed at a position separated from the P type body region.
    Type: Application
    Filed: March 25, 2004
    Publication date: September 16, 2004
    Applicant: Sanyo Electric Co., Ltd., a Osaka, Japan corporation
    Inventors: Eiji Nishibe, Shuichi Kikuchi
  • Patent number: 6786027
    Abstract: An engageable pawl member is provided so as to be swingable about a supporting shaft so that a pawl tip is movable along a moving path for a strapping band. The engageable pawl member is pulled forwardly in a swinging direction by a helical tension spring to push the pawl tip against the strapping band. The engageable pawl member shifts forwardly, following the movement of the strapping band in a feeding direction, and the strapping band is sandwiched and held between the engageable paw member and a holding guide. Then, the engageable pawl member follows the movement of the strapping band in a direction to pull back, and the engageable pawl member shifts backwardly so that the pawl tip moves in a direction out of the moving path for the strapping band.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: September 7, 2004
    Assignee: Nichiro Kogyo Co., Ltd.
    Inventors: Katsumi Oda, Tetsuya Hoshino, Shuichi Kikuchi
  • Publication number: 20040124478
    Abstract: A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 1, 2004
    Applicant: Sanyo Electric Co., Ltd., a Japanese corporation
    Inventors: Eiji Nishibe, Shuichi Kikuchi, Takuya Suzuki
  • Patent number: 6740932
    Abstract: A semiconductor device has a gate electrode formed on P type semiconductor substrate through a gate insulation film, a low concentration N− type drain region formed so as to be adjacent to the gate electrode, a high concentration N+ type drain region separated from the other end of said gate electrode and included in said low N− type drain region, and a middle concentration N type layer at a region spanning at least from said gate electrode to said high concentration N+ type drain region, and formed so that impurity concentration becomes low at a region near the gate electrode.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: May 25, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Eiji Nishibe, Takuya Suzuki
  • Patent number: 6737707
    Abstract: A transistor of a semiconductor device has an increased driving capacity. The semiconductor device has a first gate insulation film formed by a selective oxidation, a second gate insulation film formed by thermal oxidation and a gate electrode formed across the first and the second gate insulation films. The second gate insulation film is composed of a thicker gate insulation film and a thinner gate insulation film.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: May 18, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Masaaki Momen
  • Publication number: 20040089756
    Abstract: A tape reel in which molding quality of a flange unit is improved so as to improve reliability at the time when a magnetic tape runs at high speed, and a tape cartridge having the same. A plurality of reference planes (152v) formed between a chucking gear (152b) and an outer peripheral rib (152r2) formed at an outer peripheral side of this chucking gear (152b) are provided separately from the outer peripheral rib (152r2). And the reference plane (152v) is formed with edge planes of each of a first rib (152v1) extending toward a circumference and a second rib (152v2) extending toward a direction crossing the first rib (152v1). According to this arrangement, a volume at a portion constituting the reference plane (152v) is made smaller, occurrence of a sink after a resin is hardened is suppressed, and molding quality of the flange unit (152) is improved so that straight runnability of the magnetic tape at high speed running and reliability in recording/reproducing operation are improved.
    Type: Application
    Filed: September 16, 2003
    Publication date: May 13, 2004
    Inventors: Takaaki Sanpei, Shuichi Kikuchi, Kazuo Sasaki, Mitsue Sakurai, Hitomi Chiba
  • Patent number: 6713331
    Abstract: A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: March 30, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Eiji Nishibe, Shuichi Kikuchi, Takuya Suzuki
  • Publication number: 20040053471
    Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N−-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N−-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.
    Type: Application
    Filed: June 25, 2003
    Publication date: March 18, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Masafumi Uehara, Eiji Nishibe, Katsuyoshi Anzai
  • Publication number: 20040051158
    Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N−-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N−-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.
    Type: Application
    Filed: June 25, 2003
    Publication date: March 18, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Masafumi Uehara, Eiji Nishibe, Katsuyoshi Anzai