Patents by Inventor Shuichi Ueno
Shuichi Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110193185Abstract: There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge.Type: ApplicationFiled: April 18, 2011Publication date: August 11, 2011Applicant: RENESAS ELECTRONICS CORPORTIONInventors: Takashi Takenaga, Takeharu Kuroiwa, Hiroshi Takada, Shuichi Ueno, Kiyoshi Kawabata
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Patent number: 7973376Abstract: The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.Type: GrantFiled: August 28, 2009Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Haruo Furuta, Ryoji Matsuda, Shuichi Ueno, Takeharu Kuroiwa
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Publication number: 20110121419Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.Type: ApplicationFiled: February 4, 2011Publication date: May 26, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shuichi UENO, Haruo Furuta, Ryoji Matsuda, Tatsuya Fukumura, Shin Hasegawa, Shinya Hirano, Hiroyuki Chibahara, Hiroshi Oshita
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Publication number: 20110062539Abstract: To provide a semiconductor device in which the deterioration of the rewrite property is suppressed. In a memory cell region, magnetoresistive elements in a semiconductor magnetic-storage device are formed in an array shape in a mode that the magnetoresistive elements are arranged at portions where digit lines extending in one direction intersect bit lines extending in the direction approximately orthogonal to the digit lines. The digit line and the bit line have such a wiring structure constituted by covering a copper film to be a wiring main body with a cladding layer. One end side of the magnetoresistive element is electrically coupled to the bit line via a top via formed from a non-magnetic material.Type: ApplicationFiled: September 17, 2010Publication date: March 17, 2011Inventors: Ryoji MATSUDA, Motoi Ashida, Shuichi Ueno, Shoichi Fukui, Shinya Hirano, Seiji Muranaka, Kazuyuki Omori
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Patent number: 7906346Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.Type: GrantFiled: August 7, 2008Date of Patent: March 15, 2011Assignee: Renesas Electronics CorporationInventors: Shuichi Ueno, Haruo Furuta, Ryoji Matsuda, Tatsuya Fukumura, Shin Hasegawa, Shinya Hirano, Hiroyuki Chibahara, Hiroshi Oshita
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Publication number: 20100264501Abstract: Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode.Type: ApplicationFiled: February 25, 2008Publication date: October 21, 2010Inventors: Haruo Furuta, Shuichi Ueno, Ryoji Matsuda, Tatsuta Fukumura, Takeharu Kuroiwa, Lien-Chang Wang, Eugene Chen, Yiming Huai
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Publication number: 20100193831Abstract: Provided are an epoxy resin composition including acid anhydrides (A) and epoxy resins (B), in which: (a) cyclohexane-1,2,4-tricarboxylic acid-1,2-anhydride accounts for 50 to 90 mass % of the acid anhydrides (A); (b) an alicyclic epoxy resin compound accounts for 30 to 90 mass % of the epoxy resins (B) and an epoxy resin compound represented by the following general formula (1) accounts for 10 to 50 mass % of the epoxy resins (B); and (c) contents of the acid anhydrides (A) and the epoxy resins (B) are such that a blending equivalent ratio between the acid anhydrides and the epoxy resins ranges from 0.4 to 0.7, a cured product of the composition, and a light-emitting diode. The epoxy resin composition has the following characteristics.Type: ApplicationFiled: September 22, 2008Publication date: August 5, 2010Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INCInventors: Takashi Sato, Shuichi Ueno, Takeshi Koyama
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Publication number: 20090315128Abstract: The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.Type: ApplicationFiled: August 28, 2009Publication date: December 24, 2009Inventors: Haruo Furuta, Ryoji Matsuda, Shuichi Ueno, Takeharu Kuroiwa
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Publication number: 20090302404Abstract: A semiconductor device having an MTJ device excellent in operating characteristics and a manufacturing method therefor are obtained. The MTJ device is formed of a laminated structure obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower magnetic film and the upper magnetic film contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film of the MTJ device and a hard mask is formed over the CAP layer. The CAP layer contains a simple substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a simple substance of crystalline tantalum (Ta) as a constituent material. The hard mask is so formed that the film thickness thereof is larger than the film thickness of the CAP layer.Type: ApplicationFiled: May 11, 2009Publication date: December 10, 2009Inventors: Ryoji Matsuda, Shuichi Ueno, Haruo Furuta, Takashi Takenaga, Takeharu Kuroiwa
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Patent number: 7605420Abstract: The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.Type: GrantFiled: November 7, 2006Date of Patent: October 20, 2009Assignee: Renesas Technology Corp.Inventors: Haruo Furuta, Ryoji Matsuda, Shuichi Ueno, Takeharu Kuroiwa
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Publication number: 20090250776Abstract: There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge.Type: ApplicationFiled: March 6, 2009Publication date: October 8, 2009Inventors: Takashi Takenaga, Takeharu Kuroiwa, Hiroshi Takada, Shuichi Ueno, Kiyoshi Kawabata
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Publication number: 20090237989Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (1/3)·(L1/L2)?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1/L2) is satisfied.Type: ApplicationFiled: June 2, 2009Publication date: September 24, 2009Applicant: Renesas Technology CorporationInventors: Yoshinori OKUMURA, Shuichi Ueno, Haruo Furuta
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Publication number: 20090174016Abstract: A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side.Type: ApplicationFiled: January 7, 2009Publication date: July 9, 2009Inventors: Hiroaki Tanizaki, Shuichi Ueno, Yasumitsu Murai, Takaharu Tsuji
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Patent number: 7554837Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (?)·(L1/L2)?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1/L2) is satisfied.Type: GrantFiled: June 20, 2008Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Yoshinori Okumura, Shuichi Ueno, Haruo Furuta
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Publication number: 20090039451Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.Type: ApplicationFiled: August 7, 2008Publication date: February 12, 2009Inventors: Shuichi UENO, Haruo Furuta, Ryoji Matsuda, Tatsuya Fukumura, Shin Hasegawa, Shinya Hirano, Hiroyuki Chibahara, Hiroshi Oshita
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Publication number: 20080266939Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (?)·(L1/L2)?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1/L2) is satisfied.Type: ApplicationFiled: June 20, 2008Publication date: October 30, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yoshinori Okumura, Shuichi Ueno, Haruo Furuta
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Patent number: 7403415Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (?)·(L1/L2 )?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1 /L2) is satisfied.Type: GrantFiled: January 29, 2007Date of Patent: July 22, 2008Assignee: Reneasa Technology Corp.Inventors: Yoshinori Okumura, Shuichi Ueno, Haruo Furuta
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Publication number: 20080168649Abstract: A photolithographic process using an X-direction delimiting mask (S11) for aligning respective side faces of a TMR element (1) and a strap (5) situated in a negative X side is performed, to shape the TMR element (1) and the strap (5) into desired configurations. The X-direction delimiting mask (S11) includes a straight edge and is disposed such that the straight edge is parallel to a Y direction and crosses both the TMR element (1) and the strap (5) in plan view. In use of the X-direction delimiting mask (S11), respective portions of the TMR element (1) and the strap (5) situated in a positive X side relative to the straight edge in plan view are covered with the X-direction delimiting mask (S11).Type: ApplicationFiled: March 14, 2008Publication date: July 17, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Shinroku Maejima, Shuichi Ueno, Takashi Takenaga, Takeharu Kuroiwa
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Patent number: 7371882Abstract: A reactor for producing a nitrile compound from a carbon ring or heterocyclic compound having organic substituents by a gas phase reaction using a fluidized catalyst bed with ammonia and a gas containing oxygen. In a cylindrical fluidized catalyst bed having a diameter of 2.0 meters or greater, partial vaporization-type cooling tubes (the cooling medium is partially vaporized in the tubes) and complete vaporization-type cooling tubes (the cooling medium is completely vaporized in the cooling tubes) are disposed in a specific arrangement. Water containing ionic SiO2 in 0.1 ppm or smaller and having an electric conductivity of 5 ?S/cm or smaller is used as the cooling medium for the complete vaporization-type cooling tubes. The temperature of the reaction is easily stabilized and uniform distribution of temperature is obtained in the fluidized catalyst bed. Stable continuous operation is achieved for a long time in a commercial scale apparatus.Type: GrantFiled: September 15, 2004Date of Patent: May 13, 2008Assignee: Mitsubishi Gas Chemical Company, Inc.Inventors: Shuichi Ueno, Takuji Shitara, Kenichi Nakamura, Fumisada Kosuge
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Publication number: 20080039591Abstract: The present invention provides an acid anhydride ester obtained by esterifying cyclohexane-1,2,4-tricarboxylic acid-1,2-anhydride and a composition of the ester, and a heat-curable resin composition and a cured product of the composition. _Provided is an epoxy resin composition using the acid anhydride ester as a curing agent for an epoxy resin, the epoxy resin composition having, for example, the following properties (1), (2), and (3): (1) the epoxy resin composition has a low viscosity at room temperature, so the components of the composition can be favorably blended with each other, (2) the acid anhydride ester has a low vapor pressure at curing temperature, so no evaporation loss occurs after curing, and the intended design of blend is capable, and (3) a cured product to be made from the composition is colorless and transparent, and changes its color to a small extent even when the product is irradiated with light or heated for a long time period.Type: ApplicationFiled: August 8, 2007Publication date: February 14, 2008Inventors: Tomohiro Sugawara, Takeshi Koyama, Atsushi Okoshi, Takashi Sato, Shuichi Ueno