Patents by Inventor Shuichi Ueno
Shuichi Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6475844Abstract: A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.Type: GrantFiled: July 31, 2000Date of Patent: November 5, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hidekazu Oda, Tomohiro Yamashita, Shuichi Ueno
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Patent number: 6469347Abstract: MOS type semiconductor device is formed on the primary surface of a semiconductor substrate. A channel region includes a punch-through stopper layer, a lower counter-doped layer, and an upper counter-doped layer. The punch-through stopper layer is formed between the source region and the drain region and has a first concentration peak. The lower counter-doped layer is formed between the source region and the drain region, and has a second concentration peak at a position shallower than the position of the first concentration peak. Further, the upper counter-doped layer is formed between the source region and the drain region, and has a third concentration peak at a position shallower than the position of the second concentration peak. A buried-channel semiconductor device exhibits high punch-through characteristics and prevents an increase in a threshold voltage.Type: GrantFiled: April 20, 2000Date of Patent: October 22, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hidekazu Oda, Tomohiro Yamashita, Shuichi Ueno
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Patent number: 6461934Abstract: Trench isolation regions of different depths are formed through a simple manufacturing process, and reliability of a semiconductor device is increased. Trenches (103a, 103b) of different widths are formed on a semiconductor substrate (101) on which an underlying film (104) such as a silicon oxide film and a mask material (105) such as a silicon nitride film are formed. Then, an insulating film such as a silicon oxide film is deposited over the entire surface to such a degree that the narrower trench (103a) is filled up. At this time, the wider trench (103b) has an unfilled space in its central portion. a The surface of the substrate (101) is then vertically etched back until it is exposed in the trench 103b. With insulating films (106a, 106b) in the trenches (103a, 103b) as a mask, the surface of the substrate (101) is anisotropically etched vertically to form a deeper bottom (103c) in the trench (103b).Type: GrantFiled: May 23, 2001Date of Patent: October 8, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yukio Nishida, Shuichi Ueno, Masashi Kitazawa
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Publication number: 20020130374Abstract: According to a semiconductor device and a method of manufacturing the same, a trade-off relationship between threshold values and a diffusion layer leak is eliminated and it is not necessary to form gate oxide films at more than one stages. Since impurity dose are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), impurity concentration in the gate electrodes (4A to 4C) are different from each other. The impurity concentration in the gate electrodes are progressively lower in the order of higher threshold values which are expected.Type: ApplicationFiled: August 4, 1999Publication date: September 19, 2002Inventors: SHUICHI UENO, YOSHINORI OKUMURA, SHIGENOBU MAEDA, SHIGETO MAEGAWA
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Patent number: 6380036Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 Å from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.Type: GrantFiled: October 23, 2000Date of Patent: April 30, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hidekazu Oda, Shuichi Ueno, Takehisa Yamaguchi
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Publication number: 20020020870Abstract: A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n+ drain diffusion region, n-type region and p+ impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.Type: ApplicationFiled: August 29, 2001Publication date: February 21, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Shuichi Ueno, Shigeru Kusunoki, Yoshinori Okumura
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Publication number: 20010036705Abstract: Trench isolation regions of different depths are formed through a simple manufacturing process, and reliability of a semiconductor device is increased. Trenches (103a, 103b) of different widths are formed on a semiconductor substrate (101) on which an underlying film (104) such as a silicon oxide film and a mask material (105) such as a silicon nitride film are formed. Then, an insulating film such as a silicon oxide film is deposited over the entire surface to such a degree that the narrower trench (103a) is filled up. At this time, the wider trench (103b) has an unfilled space in its central portion. The surface of the substrate (101) is then vertically etched back until it is exposed in the trench 103b. With insulating films (106a, 106b) in the trenches (103a, 103b) as a mask, the surface of the substrate (101) is anisotropically etched vertically to form a deeper bottom (103c) in the trench (103b).Type: ApplicationFiled: May 23, 2001Publication date: November 1, 2001Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yukio Nishida, Shuichi Ueno, Masashi Kitazawa
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Patent number: 6300664Abstract: Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+-type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.Type: GrantFiled: June 23, 1997Date of Patent: October 9, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Kuroi, Shuichi Ueno, Hidekazu Oda, Satoshi Shimizu
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Patent number: 6300656Abstract: A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n+ drain diffusion region, n-type region and p+ impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.Type: GrantFiled: May 15, 1996Date of Patent: October 9, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shuichi Ueno, Shigeru Kusunoki, Yoshinori Okumura
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Patent number: 6255146Abstract: According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.Type: GrantFiled: October 31, 2000Date of Patent: July 3, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Shimizu, Shuichi Ueno, Shigenobu Maeda, Takashi Ipposhi
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Patent number: 6188085Abstract: According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.Type: GrantFiled: June 18, 1999Date of Patent: February 13, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Shimizu, Shuichi Ueno, Shigenobu Maeda, Takashi Ipposhi
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Patent number: 6153910Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 .ANG. from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.Type: GrantFiled: October 1, 1997Date of Patent: November 28, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hidekazu Oda, Shuichi Ueno, Takehisa Yamaguchi
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Patent number: 6130463Abstract: A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.Type: GrantFiled: July 2, 1999Date of Patent: October 10, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hidekazu Oda, Tomohiro Yamashita, Shuichi Ueno
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Patent number: 6020610Abstract: With a semiconductor device and according to a manufacturing method of the invention, a trade-off relationship between a threshold value and a diffusion layer leak is eliminated, and it is not necessary to form a gate oxide film at a plurality of steps. Gate electrodes (4A, 4B and 4C) respectively comprise a polysilicon layer (M1) and a WSi layer (L1), the polysilicon layer (M1) and a WSi layer (L2), the polysilicon layer (M1) and a WSi layer (L3), which are respectively stacked in this order on a gate oxide film (3). Channel dope layers (103A, 103B and 103C) are formed within a well layer (101) respectively under the gate electrodes (4A, 4B and 4C).Type: GrantFiled: October 7, 1997Date of Patent: February 1, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shuichi Ueno, Yoshinori Okumura, Shigenobu Maeda, Shigeto Maegawa
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Patent number: 6017781Abstract: According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.Type: GrantFiled: November 25, 1996Date of Patent: January 25, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Shimizu, Shuichi Ueno, Shigenobu Maeda, Takashi Ipposhi
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Patent number: 5998828Abstract: In a semiconductor device and a method of manufacturing the same according to the present invention, a trade-off relationship between threshold values and a diffusion layer leakage is eliminated and it is not necessary to form gate oxide films at more than one stages. Since doses of nitrogen are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), concentrations of nitrogen in the nitrogen-introduced regions (N1 to N3) are accordingly different from each other. Concentrations of nitrogen in the gate electrodes are progressively lower in the order of expected higher threshold values.Type: GrantFiled: October 27, 1997Date of Patent: December 7, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shuichi Ueno, Yoshinori Okumura, Shigenobu Maeda, Shigeto Maegawa
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Patent number: 5978294Abstract: A dummy cell part <31> includes a capacitor <311> having a first end which is connected to one of a plurality of pads <2> and a P-N junction element <312> having a first end which is connected to one of the plurality of pads <2> and a second end which is connected to one of the plurality of pads <2>. A sense part <32> is connected to a second end of the capacitor <311>, for sensing a potential on the second end of the capacitor <311> and outputting the result of sensing to one of the plurality of pads <2>. Thus, a memory cell evaluation semiconductor device which can evaluate a single memory cell, a method of fabricating the same and a memory cell evaluation method are obtained.Type: GrantFiled: July 9, 1998Date of Patent: November 2, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shuichi Ueno, Tomohiro Yamashita, Hidekazu Oda, Shigeki Komori
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Patent number: 5600154Abstract: According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.Type: GrantFiled: October 20, 1995Date of Patent: February 4, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Shimizu, Shuichi Ueno, Shigenobu Maeda, Takashi Ipposhi
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Patent number: 5557129Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 .ANG. from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.Type: GrantFiled: May 25, 1995Date of Patent: September 17, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hidekazu Oda, Shuichi Ueno, Takehisa Yamaguchi
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Patent number: 5192016Abstract: A method of manufacturing tubes filled with powdery and/or granular substances, such as flux-cored welding wires. A tube filled with a powdery and/or granular substance is continuously manufactured by forming a metal strip being fed in its longitudinal direction into an unwelded tube (1a) using forming rolls (2), feeding a powdery and/or granular substance (F) into the unwelded tube (1a) being formed through its opening, butt-welding together fringing edges of the opening, and reducing the diameter of the welded tube (1b). An allowable minimum heat input below which cold cracking occurs and a maximum allowable heat input above which spatters whose diameter is not smaller than 0.83 times the inside diameter of the finished tube are generated are determined in advance, and the butt welding is performed with a heat input larger than the allowable minimum heat input and smaller than the allowable maximum heat input.Type: GrantFiled: February 21, 1992Date of Patent: March 9, 1993Assignees: Nippon Steel Corporation, Nippon Steel Welding Products & Engineering Co., Ltd.Inventors: Nobuo Araki, Takeji Kagami, Yoji Chatani, Shunichi Kikuta, Iwao Yamada, Masao Kamada, Seiji Hashimoto, Shuichi Ueno, Takeshi Fukui, Takumi Nakamura, Nobuo Mizuhashi, Yasushi Ishikawa