Patents by Inventor Shuichi Ueno
Shuichi Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070139999Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (1/3)·(L1/L2)?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1/L2) is satisfied.Type: ApplicationFiled: January 29, 2007Publication date: June 21, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yoshinori Okumura, Shuichi Ueno, Haruo Furuta
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Publication number: 20070108543Abstract: The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.Type: ApplicationFiled: November 7, 2006Publication date: May 17, 2007Inventors: Haruo Furuta, Ryoji Matsuda, Shuichi Ueno, Takeharu Kuroiwa
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Patent number: 7180773Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (?)·(L1/L2)?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1/L2) is satisfied.Type: GrantFiled: October 20, 2005Date of Patent: February 20, 2007Assignee: Renesas Technology Corp.Inventors: Yoshinori Okumura, Shuichi Ueno, Haruo Furuta
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Patent number: 7157773Abstract: A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.Type: GrantFiled: December 30, 2002Date of Patent: January 2, 2007Assignee: Renesas Technology Corp.Inventors: Hiroshi Kato, Shigehiro Kuge, Hideyuki Noda, Fukashi Morishita, Shuichi Ueno
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Publication number: 20060087874Abstract: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2?1, a relation of (?)·(L1/L2)?S2/S1?1 is satisfied and when L1/L2?1, a relation of 1?S2/S1?3(L1/L2) is satisfied.Type: ApplicationFiled: October 20, 2005Publication date: April 27, 2006Inventors: Yoshinori Okumura, Shuichi Ueno, Haruo Furuta
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Patent number: 6897523Abstract: A semiconductor device is provided which includes a diode formed of a MISFET and having a current-voltage characteristic close to that of an ideal diode. Negatively charged particles (e.g. electrons: 8a) are trapped on the drain region (2) side of a silicon nitride film (4b) sandwiched between films of silicon oxide (4a, 4c). When a bias voltage is applied between the drain and source with the negatively charged particles (8a) thus trapped and in-channel charged particles (9a) induced by them, the MISFET exhibits different threshold values for channel formation depending on whether it is a forward bias or a reverse bias. That is to say, when a reverse bias is applied, the channel forms insufficiently and the source-drain current is less likely to flow, while the channel forms sufficiently and a large source-drain current flows when a forward bias is applied. This offers a current-voltage characteristic close to that of the ideal diode.Type: GrantFiled: August 5, 2002Date of Patent: May 24, 2005Assignee: Renesas Technology Corp.Inventors: Shuichi Ueno, Haruo Furuta, Shigehiro Kuge, Hiroshi Kato
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Publication number: 20050054855Abstract: A reactor for producing a nitrile compound from a carbon ring or heterocyclic compound having organic substituents by a gas phase reaction using a fluidized catalyst bed with ammonia and a gas containing oxygen. In a cylindrical fluidized catalyst bed having a diameter of 2.0 meters or greater, partial vaporization-type cooling tubes (the cooling medium is partially vaporized in the tubes) and complete vaporization-type cooling tubes (the cooling medium is completely vaporized in the cooling tubes) are disposed in a specific arrangement. Water containing ionic SiO2 in 0.1 ppm or smaller and having an electric conductivity of 5 ?S/cm or smaller is used as the cooling medium for the complete vaporization-type cooling tubes. The temperature of the reaction is easily stabilized and uniform distribution of temperature is obtained in the fluidized catalyst bed. Stable continuous operation is achieved for a long time in a commercial scale apparatus.Type: ApplicationFiled: September 15, 2004Publication date: March 10, 2005Inventors: Shuichi Ueno, Takuji Shitara, Kenichi Nakamura, Fumisada Kosuge
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Publication number: 20040246777Abstract: A photolithographic process using an X-direction delimiting mask (S11) for aligning respective side faces of a TMR element (1) and a strap (5) situated in a negative X side is performed, to shape the TMR element (1) and the strap (5) into desired configurations. The X-direction delimiting mask (S11) includes a straight edge and is disposed such that the straight edge is parallel to a Y direction and crosses both the TMR element (1) and the strap (5) in plan view. In use of the X-direction delimiting mask (S11), respective portions of the TMR element (1) and the strap (5) situated in a positive X side relative to the straight edge in plan view are covered with the X-direction delimiting mask (S11).Type: ApplicationFiled: March 25, 2004Publication date: December 9, 2004Inventors: Shinroku Maejima, Shuichi Ueno, Takashi Takenaga, Takeharu Kuroiwa
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Patent number: 6815295Abstract: In a semiconductor device and a method of manufacturing the same according to the present invention, a trade-off relationship between threshold values and a diffusion layer leakage is eliminated and it is not necessary to form gate oxide films at more than one stages. Since doses of nitrogen are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), concentrations of nitrogen in the nitrogen-introduced regions (N1 to N3) are accordingly different from each other. Concentrations of nitrogen in the gate electrodes are progressively lower in the order of expected higher threshold values.Type: GrantFiled: October 28, 1999Date of Patent: November 9, 2004Assignee: Renesas Technology Corp.Inventors: Shuichi Ueno, Yoshinori Okumura, Shigenobu Maeda, Shigeto Maegawa
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Patent number: 6812536Abstract: A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.Type: GrantFiled: March 10, 2003Date of Patent: November 2, 2004Assignee: Renesas Technology Corp.Inventors: Shuichi Ueno, Yukio Nishida, Hiroshi Umeda, Kenichi Ohto, Takashi Terauchi, Shigeru Shiratake, Akinori Kinugasa
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Publication number: 20040185609Abstract: A semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor substrate, and moreover, has little deterioration of an electrical characteristic in the structure that a sidewall insulating film in a shared contact plug part is removed is provided. An active layer (16) is formed by performing an additional impurity injection on a part where a sidewall insulating film is removed in a forming portion of a shared contact plug (18a). An insulating film is laminated in a high voltage circuit part (AR1) and a sidewall insulating film (10d) of wide width is formed. According to this, a forming width of a sidewall insulating film (10a) can be made small in a MOS transistor for a memory cell part (AR2), and a forming width of a sidewall insulating film (10d) can be made large in a MOS transistor for a high voltage circuit part.Type: ApplicationFiled: April 1, 2004Publication date: September 23, 2004Applicant: Renesas Technology Corp.Inventors: Yoshinori Okumura, Shuichi Ueno, Haruo Furuta
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Patent number: 6770522Abstract: A semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor substrate, and moreover, has little deterioration of an electric characteristic in the structure that a sidewall insulating film in a shared contact plug part is removed is provided. An active layer is formed by performing an additional impurity injection on a part where a sidewall insulating film is removed in a forming portion of a shared contact plug. An insulating film is laminated in a high voltage circuit part and a sidewall insulating film of wide width is formed. According to this, a forming width of a sidewall insulating film can be made small in a MOS transistor for a memory cell part, and a forming width of a sidewall insulating film can be made large in a MOS transistor for a high voltage circuit part.Type: GrantFiled: May 27, 2003Date of Patent: August 3, 2004Assignee: Renesas Technology Corp.Inventors: Yoshinori Okumura, Shuichi Ueno, Haruo Furuta
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Publication number: 20040092063Abstract: A semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor substrate, and moreover, has little deterioration of an electrical characteristic in the structure that a sidewall insulating film in a shared contact plug part is removed is provided. An active layer (16) is formed by performing an additional impurity injection on a part where a sidewall insulating film is removed in a forming portion of a shared contact plug (18a). An insulating film is laminated in a high voltage circuit part (AR1) and a sidewall insulating film (10d) of wide width is formed. According to this, a forming width of a sidewall insulating film (10a) can be made small in a MOS transistor for a memory cell part (AR2), and a forming width of a sidewall insulating film (10d) can be made large in a MOS transistor for a high voltage circuit part.Type: ApplicationFiled: May 27, 2003Publication date: May 13, 2004Applicant: Renesas Technology Corp.Inventors: Yoshinori Okumura, Shuichi Ueno, Haruo Furuta
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Patent number: 6731535Abstract: A nonvolatile semiconductor memory device includes a silicon substrate, bit lines, word lines, and memory cells. The bit line is positioned above the main surface of the silicon substrate and the word line is provided to intersect the bit line. The memory cell is positioned at a region where the bit line and the word line intersect and has one end electrically connected to the bit line and the other end electrically connected to the word line. The memory cell includes a TMR element and an access diode electrically connected in series. The access diode includes an n-type silicon layer and a p-type silicon layer recrystallized by melting-recrystallization and has a pn junction at the interface between the n-type silicon layer and the p-type silicon layer. As a result, a nonvolatile semiconductor memory device reduced in size and having high performance can be manufactured inexpensively.Type: GrantFiled: June 6, 2003Date of Patent: May 4, 2004Assignee: Renesas Technology Corp.Inventors: Tsukasa Ooishi, Shuichi Ueno, Shigehiro Kuge
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Publication number: 20040046219Abstract: A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.Type: ApplicationFiled: March 10, 2003Publication date: March 11, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Shuichi Ueno, Yukio Nishida, Hiroshi Umeda, Kenichi Ohto, Takashi Terauchi, Shigeru Shiratake, Akinori Kinugasa
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Publication number: 20040007734Abstract: A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.Type: ApplicationFiled: December 30, 2002Publication date: January 15, 2004Inventors: Hiroshi Kato, Shigehiro Kuge, Hideyuki Noda, Fukashi Morishita, Shuichi Ueno
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Publication number: 20040005254Abstract: A reactor for producing a nitrile compound from a carbon ring or heterocyclic compound having organic substituents by a gas phase reaction using a fluidized catalyst bed with ammonia and a gas containing oxygen. In a cylindrical fluidized catalyst bed having a diameter of 2.0 meters or greater, partial vaporization-type cooling tubes (the cooling medium is partially vaporized in the tubes) and complete vaporization-type cooling tubes (the cooling medium is completely vaporized in the cooling tubes) are disposed in a specific arrangement. Water containing ionic SiO2 in 0.1 ppm or smaller and having an electric conductivity of 5 &mgr;S/cm or smaller is used as the cooling medium for the complete vaporization-type cooling tubes. The temperature of the reaction is easily stabilized and uniform distribution of temperature is obtained in the fluidized catalyst bed. Stable continuous operation is achieved for a long time in a commercial scale apparatus.Type: ApplicationFiled: December 23, 2002Publication date: January 8, 2004Inventors: Shuichi Ueno, Takuji Shitara, Kenichi Nakamura, Fumisada Kosuge
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Publication number: 20030151086Abstract: A semiconductor device is provided which includes a diode formed of a MISFET and having a current-voltage characteristic close to that of an ideal diode. Negatively charged particles (e.g. electrons: 8a) are trapped on the drain region (2) side of a silicon nitride film (4b) sandwiched between films of silicon oxide (4a, 4c). When a bias voltage is applied between the drain and source with the negatively charged particles (8a) thus trapped and in-channel charged particles (9a) induced by them, the MISFET exhibits different threshold values for channel formation depending on whether it is a forward bias or a reverse bias. That is to say, when a reverse bias is applied, the channel forms insufficiently and the source-drain current is less likely to flow, while the channel forms sufficiently and a large source-drain current flows when a forward bias is applied. This offers a current-voltage characteristic close to that of the ideal diode.Type: ApplicationFiled: August 5, 2002Publication date: August 14, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Shuichi Ueno, Haruo Furuta, Shigehiro Kuge, Hiroshi Kato
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Patent number: 6521527Abstract: Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+-type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.Type: GrantFiled: August 7, 2001Date of Patent: February 18, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Kuroi, Shuichi Ueno, Hidekazu Oda, Satoshi Shimizu
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Patent number: 6492690Abstract: According to a semiconductor device and a method of manufacturing the same, a trade-off relationship between threshold values and a diffusion layer leak is eliminated and it is not necessary to form gate oxide films at more than one stages. Since impurity dose are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), impurity concentration in the gate electrodes (4A to 4C) are different from each other. The impurity concentration in the gate electrodes are progressively lower in the order of higher threshold values which are expected.Type: GrantFiled: August 4, 1999Date of Patent: December 10, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shuichi Ueno, Yoshinori Okumura, Shigenobu Maeda, Shigeto Maegawa