Patents by Inventor Shun Wu

Shun Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6653280
    Abstract: An antifungal polypeptide, AlyAFP, that controls fungal damage to plants is provided. DNA encoding this polypeptide can be cloned into vectors for transformation of plant-colonizing microorganisms or plants, thereby providing a method of inhibiting fungal growth on plants. The polypeptide can be formulated into compositions that can be used to control undesired fungi on plants and elsewhere.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: November 25, 2003
    Assignee: Monsanto Technology LLC
    Inventors: Jihong Liang, Dilip Maganlal Shah, Yonnie Shun Wu, Cindy Annette Rosenberger
  • Patent number: 6565984
    Abstract: We have discovered that the formation of particulate inclusions at the surface and the interior of an aluminum alloy article interferes with the performance of the article when a surface of the article is protected by an anodized coating. We have also discovered that the formation of such particulate inclusions can be controlled to a large extent by controlling the concentration of particular impurities present in the alloy used to fabricate the aluminum alloy article.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: May 20, 2003
    Assignee: Applied Materials Inc.
    Inventors: Shun Wu, Clifford Stow, Hong Wang, Yixing Lin
  • Publication number: 20020160348
    Abstract: Keywords: computer assisted test, test assessment, test collection, distant learning. The main problem with the network test base system is that there are neither sufficiently many nor good enough test items. To satisfy these two points, there must be more test item resources and a mechanism for assessing test items to determine whether a test item should stay in the test base. The present invention provides a method for automation of dynamic test item collection and assessment, which allows teacher and students to contribute test items to the test base and each independently managed test base can share test items. This can make the test base rapidly grow and expand the size of a test base. The more independent the student are, the higher the applicability of this method is.
    Type: Application
    Filed: March 29, 2002
    Publication date: October 31, 2002
    Applicant: National Science Council of Republic of China
    Inventors: Ying-Dar Lin, Tsung-Shun Wu, Huan-Yun Wei, Chien Chou
  • Publication number: 20020144306
    Abstract: An antifungal polypeptide, AlyAFP, that controls fungal damage to plants is provided. DNA encoding this polypeptide can be cloned into vectors for transformation of plant-colonizing microorganisms or plants, thereby providing a method of inhibiting fungal growth on plants. The polypeptide can be formulated into compositions that can be used to control undesired fungi on plants and elsewhere.
    Type: Application
    Filed: April 9, 2001
    Publication date: October 3, 2002
    Applicant: Monsanto Company
    Inventors: Jihong Liang, Dilip Maganlal Shah, Yonnie Shun Wu, Cindy Annette Rosenberger
  • Patent number: 6219857
    Abstract: A sensor device includes a mounting frame having open front and rear ends, and right and left inner side walls opposite to each other in a longitudinal direction and extending between the front and rear ends so as to define a passage. The mounting frame is adapted to be mounted such that the body of a user of the sanitary apparatus will be sighted by the passage. A sensor body is inserted into the passage, and has a front side proximate to the front end to emit and receive a light signal, and right and left lateral walls that face respectively and spacedly the right and left inner side walls. A pair. of pivotally mounting members are respectively disposed between the right lateral and inner side walls, and between the left lateral and inner side walls such that the pivotally mounting members effect pivotal mountings which are pivotable between angular positions about an axis parallel to the longitudinal direction.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: April 24, 2001
    Assignee: Hydrotek Corporation
    Inventor: Shui-Shun Wu
  • Patent number: 6215048
    Abstract: Isolated DNA molecules encoding an AlyAFP antifungal polypeptide from Alyssum are disclosed. The isolated DNA molecules comprise the nucleotide sequence of SEQ ID NO:12 or encode the amino acid sequence of SEQ ID NO:2. Also disclosed are vectors and transgenic plants comprising said DNA molecules and a method for reducing fungal damage in a plant with said DNA molecule. The isolated DNA molecules may be used to prepare transgenic plants that exhibit reduced damage from fungi as compared to non-transgenic plants. The isolated DNA molecules may be used in combination with additional nucleic acid sequences encoding anti-fungal or anti-insect proteins or polypeptides.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: April 10, 2001
    Assignee: Monsanto Company
    Inventors: Jihong Liang, Dilip Maganlal Shah, Yonnie Shun Wu, Cindy Annette Rosenberger
  • Patent number: 6199927
    Abstract: The amount of particulate contamination produced due to rubbing between a semiconductor substrate and the robotic substrate handling blade has been greatly reduced by the use of specialized materials either as the principal material of construction for the semiconductor substrate handling blade, or as a coating upon the surface of the substrate handling blade. In particular, the specialized material must exhibit the desired stiffness at temperatures in excess of about 450° C.; the specialized material must also have an abrasion resistant surface which does not produce particulates when rubbed against the semiconductor substrate. The abrasion resistant surface needs to be very smooth, having a surface finish of less than 1.0 micro inch, and preferably less than 0.2 micro inch. In addition, the surface must be essentially void-free. In the most preferred embodiments, the upper, top surface of the substrate handling blade is constructed from a dielectric material being smooth, non-porous, and wear-resistant.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: March 13, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Behzad Shamlou, Wen Chiang Tu, Xuyen Pham, Yu Chang, Daniel O. Clark, Shun Wu
  • Patent number: 6024393
    Abstract: The amount of particulate contamination produced due to rubbing between a semiconductor substrate and the robotic substrate handling blade has been greatly reduced by the use of specialized materials either as the principal material of construction for the semiconductor substrate handling blade, or as a coating upon the surface of the wafer handling blade. In particular, the specialized material must exhibit the desired stiffness at temperatures in excess of about 450.degree. C.; the specialized material must also have an abrasion resistant surface which does not produce particulates when rubbed against the semiconductor substrate. The abrasion resistant surface needs to be very smooth, having a surface finish of less than 1.0 micro inch, and preferably less than 0.2 micro inch. In addition, the surface must be essentially void-free. In the most preferred embodiments, the upper, top surface of the substrate handling blade is constructed from a dielectric material being smooth, non-porous, and wear-resistant.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: February 15, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Behzad Shamlou, Wen Chiang Tu, Xuyen Pham, Yu Chang, Daniel O. Clark, Shun Wu
  • Patent number: 5852315
    Abstract: A MOS transistor cell is disclosed for a multiple cell MOS transistor, such as in an ESD protection circuit, output buffer, etc. The transistor cell has a regular n-sided polygonal geometry, wherein n.gtoreq.8. A drain region is provided in a substrate which occupies an area with n-sided polygonal shaped boundaries. Surrounding the drain, is a channel region which occupies an n-sided polygonal shaped area. Surrounding the channel region is a source region provided in the substrate which occupies an annular shaped area having n-sided polygonal boundaries.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: December 22, 1998
    Inventors: Ming-Dou Ker, Tain-Shun Wu, Kuo-Feng Wang
  • Patent number: 5850159
    Abstract: An output buffer is provided which receives an input signal for output onto an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage corresponding to a logic value of the input signal. The second driver has a higher driving capacity than the first driver. The output buffer also has control circuitry receiving a transition in logic value of the input signal and at least one mode signal. The control circuitry responds to the transition in logic value by delaying the second driver from driving the output terminal to a complementary voltage until after the first driver begins to drive the output terminal to the complementary voltage. In so doing, the control circuitry delays the second driver by a first delay, when the mode signal(s) indicates a full speed mode. On the other hand, the control circuitry delays the second driver by a second delay, that is longer than the first delay, when the mode signal(s) indicates a low speed mode.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: December 15, 1998
    Inventors: Hwang-Cherng Chow, Chen-Yi Huang, Tain-Shun Wu
  • Patent number: 5773696
    Abstract: An antifungal polypeptide, AlyAFP, that controls fungal damage to plants is provided. DNA encoding this polypeptide can be cloned into vectors for transformation of plant-colonizing microorganisms or plants, thereby providing a method of inhibiting fungal growth on plants. The polypeptide can be formulated into compositions that can be used to control undesired fungi on plants and elsewhere.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: June 30, 1998
    Assignee: Monsanto Company
    Inventors: Jihong Liang, Dilip Maganlal Shah, Yonnie Shun Wu, Cindy Annette Rosenberger
  • Patent number: 5757242
    Abstract: A low power consumption oscillator circuit is provided with an oscillator. The oscillator responds to a voltage by producing an oscillating signal at its output having an amplitude that depends on the level of the voltage. Furthermore, the low power consumption oscillator circuit has a level shifter. Illustratively, according to one embodiment, the level shifter includes a pull-up driver and a pull-down driver connected in parallel between the oscillator output and an output of the level shifter. The pull-up driver is configured so as to refrain from conducting current between a biasing input of the pull-up driver and the level shifter output simultaneously with the pull-down driver when the oscillating signal exceeds a certain voltage level. The level shifter illustratively includes an intrinsic PMOS device.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: May 26, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Hwang-Cherng Chow, Tain-Shun Wu
  • Patent number: 5754380
    Abstract: An ESD protection circuit for use in a CMOS output buffer circuit has been disclosed. The ESD protection circuit provides a high ESD failure threshold in a small layout area to protect the output buffer against ESD failure. The output buffer includes a pull-up PMOS device and pull-down NMOS device whose common drain is connected to an output pad. The source of the PMOS device is connected to VDD and the source of NMOS device is connected to VSS. The ESD protection circuit is formed by a PTLSCR device and an NTLSCR device. The PTLSCR (NTLSCR) is formed by inserting a short-channel thin-oxide PMOS (NMOS) device into a lateral SCR structure. These MOS devices reduce the turn-on voltage of the lateral SCR to the snapback breakdown voltage of the MOS rather than the original switching voltage of the SCR. The ESD protection circuit also includes two parasitic diodes D.sub.p between output pad and VDD and D.sub.n between output pad and VSS.
    Type: Grant
    Filed: April 6, 1995
    Date of Patent: May 19, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Dou Ker, Tain-Shun Wu
  • Patent number: 5637900
    Abstract: An ESD protection circuit fully protects the input stage of CMOS integrated circuits from four different ESD stress modes by providing four different ESD direct discharging paths. The ESD protection circuit has a primary ESD protection circuit, which has a first and a second thick-oxide MOS devices, and a secondary ESD protection circuit which has a resistor, a first and a second thin-oxide MOS devices. The resistor is connected between the primary and secondary ESD protection circuits. The primary and secondary ESD protection circuits each provide two ESD discharge paths from the input pad, and from the input of the internal circuits to be protected, to VDD and VSS voltage supply buses. The inventive ESD protection circuit also has merged latchup guard rings and protects against large ESDs, while occupying only a small layout area. Furthermore, the inventive ESD protection circuit clamps the voltage level of the input signal between 5.
    Type: Grant
    Filed: April 6, 1995
    Date of Patent: June 10, 1997
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Dou Ker, Tain-Shun Wu
  • Patent number: 5572394
    Abstract: An on-chip ESD protection circuit for use in a submicron CMOS integrated circuit (IC) has been disclosed. The ESD protection circuit provides a high ESD failure threshold in a small layout area to protect the input stage of the submicron CMOS IC against ESD failure. The ESD protection circuit is formed by a PTLSCR1, PTLSCR2 devices and an NTLSCR1, NTLSCR2 devices. The PTLSCR1 or PTLSCR2 (NTLSCR1 or NTLSCR2) is formed by inserting a short-channel thin-oxide PMOS (NMOS) device into the lateral SCR structure. These MOS devices are used to reduce the turn-on voltage of the lateral SCR to below the gate-oxide breakdown voltage of the CMOS devices in the input stage. Thus these PTLSCR1, PTLSCR2, NTLSCR1 and NTLSCR2 devices perform full ESD protection without additional secondary ESD protection elements. The four modes of ESD, PS, NS, PD and ND, are one-by-one protected by the NTLSCR1, NTLSCR2, PTLSCR1 and PTLSCR2 devices respectively.
    Type: Grant
    Filed: April 6, 1995
    Date of Patent: November 5, 1996
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Dou Ker, Tain-Shun Wu
  • Patent number: 4863375
    Abstract: This invention relates to a method of using a liquid or powder varnishing furnace utilizing near-ultrared bulbs to form high temperature regions and low temperature regions which are alternatively disposed and spaced apart by a fixed distance to heat a cleaned and painted workpiece, whereby the workpiece is dried rapidly and paint sprayed onto the workpiece firmly adheres thereto.
    Type: Grant
    Filed: May 2, 1988
    Date of Patent: September 5, 1989
    Inventor: Ching-Shun Wu