Abstract: The present invention relates to a wireless communication receiver, wireless communication receiving method and television receiver. The wireless communication receiver has signal processing circuits including a first signal processing circuit and a second signal processing circuit, a data storage module, and a deinterleaver. The first signal processing circuit receives a wireless communication signal and then performs a first signal processing to generate a first output data according to the wireless communication signal. The deinterleaver stores the first output data into the data storage module, and retrieves a deinterleaved data corresponding to the first output signal from the data storage module. The second signal processing circuit performs a second signal processing to generate a second output data according to the deinterleaved data.

Abstract: An apparatus of processing a time domain synchronous orthogonal frequency-division-multiplexing (TDS-OFDM) signal is provided. The apparatus includes a receiving block and a demodulating block. The receiving block receives the TDS-OFDM signal, and generates a down-converted signal according to the received TDS-OFDM signal. The demodulating block is coupled to the receiving block, and demodulates the down-converted signal to generate a transport stream. The demodulating block has a transmission parameter signaling (TPS) decoder implemented for performing a TPS decoding operation to generate a TPS decoding result and verifying a spectrum direction of the received TDS-OFDM signal according to the TPS decoding result.

Abstract: A multi-layer pad structure through needle punching working procedure is provided. The multi-layer pad structure comprises: a material layer which is a wrap knitted fabric with at least one mesh; and a base layer, which is a non-woven fabric surface composed of a needle punching cotton silk fiber, combined with the material layer tightly by embedding the needle punching cotton silk fiber into the material layer through needle punching working procedure. Accordingly, the defects of poor gluing level, high gluing cost, easy-deteriorated glue and non-environmentally protection existed in the previous multi-layer pad structure products can be improved.

Abstract: A semiconductor device design system comprising at least one processor is configured to define a resistance-capacitance (RC) extraction tool for determining a distance between first and second through-semiconductor-vias extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second through-semiconductor-vias in the semiconductor substrate. The semiconductor device design system comprising the at least one processor is also configured to extract parasitic parameters of a coupling in the semiconductor substrate based on the distance determined by the RC extraction tool and a model of the coupling included in a simulation tool.

Abstract: A manufacturing method of a light emitting device is provided. A first electrode is formed on a substrate. The first electrode includes a patterned conductive layer, and the patterned conductive layer includes an alloy containing a first metal and a second metal. An annealing process is performed on the first electrode, so as to form a passivation layer at least on a side surface of the first electrode. The passivation layer includes a compound of the second metal. A light emitting layer is formed on the first electrode. A second electrode is formed on the light emitting layer.

Abstract: A semiconductor device, disposed on a substrate, includes a first channel layer, a patterned doped layer, a gate insulating layer, a conducting gate electrode, a second channel layer, a first electrode and a second electrode, and a third electrode and a fourth electrode. The first channel layer is disposed on the substrate and in a first region. The patterned doped layer includes a doped gate electrode disposed in a second region, and two contact electrodes electrically connected to two sides of the first channel layer, respectively. The conducting gate electrode is disposed on the gate insulating layer in the first region. The second channel layer is disposed on the gate insulating layer in the second region. The first electrode and the second electrode are electrically connected to the contact electrodes, respectively. The third electrode and the fourth electrode are electrically connected to two sides of the second channel layer, respectively.

Abstract: An LED lamp includes a supporting base and a reflector having a plurality of reflecting tabs mounted thereon. The reflector includes many circumferentially arranged tabs around a central axis of the supporting base. Many LED light sources are mounted in the supporting base and divided into an outer array and an inner array. Each reflecting tab has a fixed end connected to the supporting base and a free end distant from the supporting base. Each reflecting tab extends upwardly and outwardly from a central portion of the supporting base toward an outer periphery thereof. The inner array of the LED light sources is surrounded by the reflector. A hole is defined in a free end of each reflecting tab and aligned with one of the LED light sources of the outer array. A lamp mounting base is also provided.

Abstract: A light emitting device is provided. A light emitting device that includes a substrate, a first electrode, a passivation layer, a second electrode, and a light emitting layer is provided. The first electrode is disposed on the substrate and includes a first patterned conductive layer. The first patterned conductive layer includes an alloy containing a first metal and a second metal. The passivation layer is at least disposed on a side surface of the first electrode and includes a compound of the second metal. Here, a work function of the compound of the second metal ranges from about 4.8 to about 5.5. The second electrode is disposed on the first electrode. The light emitting layer is disposed between the first electrode and the second electrode.

Abstract: In a semiconductor device design method performed by at least one processor, first and second electrical components are extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second electrical components in the semiconductor substrate. Parasitic parameters of a coupling in the semiconductor substrate between the first and second electrical components are extracted using a first tool. Intrinsic parameters of the first and second electrical components are extracted using a second tool different from the first tool. The extracted parasitic parameters and intrinsic parameters are combined into a model of the semiconductor device. The parasitic parameters of the coupling are extracted based on a model of the coupling included in the second tool.

Abstract: A car roof storage compartment includes a bottom member shaped as one half of a clamshell; a top member shaped as the other half of the clamshell, and a closed-end zipper. The edge of the bottom opening of the top member is combined with the bottom member at the position that lower than the top opening of the bottom member by sliding the closed-end zipper, that can prevent rain from entering the car roof storage compartment. The closed-end zipper can be slid in a desired direction in order to change the opening side of the top member. This can increase use convenience. The top member can be separated from the bottom member. Thereafter, the top members and the bottom members can be separated respectively for stacking storage purpose. This has the advantages of facilitating storage, decreasing volume, saving storage space, and decreasing transportation cost for distribution.

Abstract: Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.

Abstract: A signal transceiving module includes: a first antenna; a first signal port; and a first processing circuit coupled to the first signal port and arranged to detect a first signal quality of a first received signal received from the first signal port and determine if the first antenna is coupled to the first signal port correctly according to at least the first signal quality.

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract: Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.

Abstract: A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract: Method for dynamically controlling data paths of Machine-type-communication (MTC) local access device(s) are proposed along with a MTC gateway and a network device using the same method. In one embodiment, the proposed method may include following: a network device, receiving and storing capillary network information and MTC gateway interconnection information from at least one MTC server; combining the access network information with the capillary network information and the MTC gateway interconnection information to build an aggregated topology map; generating enhanced policy rules according to the aggregated topology map related to at least one capillary network; and respectively transmitting the enhanced policy rules to the interconnected MTC gateways.

Abstract: A manufacturing method of a light emitting device is provided. A first electrode is formed on a substrate. The first electrode includes a patterned conductive layer, and the patterned conductive layer includes an alloy containing a first metal and a second metal. An annealing process is performed on the first electrode, so as to form a passivation layer at least on a side surface of the first electrode. The passivation layer includes a compound of the second metal. A light emitting layer is formed on the first electrode. A second electrode is formed on the light emitting layer.

Abstract: A light emitting device is provided. A light emitting device that includes a substrate, a first electrode, a passivation layer, a second electrode, and a light emitting layer is provided. The first electrode is disposed on the substrate and includes a first patterned conductive layer. The first patterned conductive layer includes an alloy containing a first metal and a second metal. The passivation layer is at least disposed on a side surface of the first electrode and includes a compound of the second metal. Here, a work function of the compound of the second metal ranges from about 4.8 to about 5.5. The second electrode is disposed on the first electrode. The light emitting layer is disposed between the first electrode and the second electrode.

Abstract: A lighting module is provided. The lighting module comprises a circuit board, a first light source array, a second light source array, and a plurality of first light guides. The first light source array is disposed on the circuit board and comprises a plurality of first solid light emitting semiconductors providing a first light with a first wavelength. The second light source array is disposed on the circuit board and comprises a plurality of second solid light emitting semiconductors providing a second light with a second wavelength. The first light guides are disposed on the circuit board and between the second solid light emitting semiconductors. The second solid light emitting semiconductors are located on a side of each of the first light guides, respectively, so that the second light emitted by the second solid light emitting semiconductors enters the first light guides to be uniformly emitted.