Patents by Inventor Shun Yang

Shun Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180084550
    Abstract: Various solutions for data transmission over multiple uplink carrier with respect to user equipment (UE) in mobile communications are described. A UE may establish a connection over a downlink component carrier and a first uplink component carrier with a network apparatus. The UE may further establish a connection over a second uplink component carrier with the network apparatus. The UE may transmit uplink data to the network apparatus via at least one of the first uplink component carrier and the second uplink component carrier. The UE may also assign the first uplink component carrier as a primary carrier and assigning the second uplink component carrier as a supplementary carrier. The UE may further switch the primary carrier from the first uplink component carrier to the second uplink component carrier.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 22, 2018
    Inventors: Yih-Shen Chen, Shun-An Yang, Chih Hsiu Lin, Guan-Yu Lin
  • Publication number: 20180063972
    Abstract: A sliding structure for stacked electric power modules is provided. The sliding structure includes a left slide structure and a right slide structure extending in a movement direction at a left top edge and a right top edge of the electric power module respectively. A left bottom edge and a right bottom edge of each electric power module are respectively provided with a counterpart left slide structure and a counterpart right slide structure extending in the movement direction and corresponding to the left slide structure and the right slide structure respectively. Multiple electric power modules are allowed to be stacked through the sliding structure.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 1, 2018
    Inventor: KUO-SHUN YANG
  • Publication number: 20180062145
    Abstract: A connector assembly is provided for stacked electric power modules. Each of the electric power modules includes a front board, a back board, a top board, a bottom board, a left side board, a right side board, and a battery pack contained in the electric power module. The back board of the electric power module includes a connector module mounted thereto and the connector module includes at least one power connector connected to the battery pack and at least one signal connector. The at least one power connector and the at least one signal connector of the connector module are arranged to project beyond a horizontal surface of the top board.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 1, 2018
    Inventor: KUO-SHUN YANG
  • Publication number: 20180046744
    Abstract: The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments, the method also includes rearranging a first cell to abut the first cell with a second cell when the first cell placement fails to satisfy design demands. In still further embodiments, the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined. In various embodiments, the method further includes generating a design layout based on the second cell placement and outputting the design layout to a machine readable storage medium. The outputted layout is used to manufacture a set of masks used in chip fabrication processes.
    Type: Application
    Filed: October 26, 2016
    Publication date: February 15, 2018
    Inventors: Wan-Ru Lin, Ching-Shun Yang
  • Publication number: 20170341706
    Abstract: A charge system and a charge method adapted to a bicycle are provided. The charge system includes a hub dynamo, a power apparatus, a sensor and a control apparatus. The control apparatus is coupled to the hub dynamo, the power apparatus and the sensor. The sensor is adapted to sense a riding condition of the bicycle. According to the riding condition, the control apparatus selects a power supply pattern of the hub dynamo. When the power supply pattern is selected to be a stop pattern, a connection loop between the hub dynamo and the power apparatus is turned off by the control apparatus. When the power supply pattern is selected to a first pattern, the connection loop between the hub dynamo and the power apparatus is turned on by the control apparatus, such that the hub dynamo supplies power to the power apparatus at a first rate.
    Type: Application
    Filed: December 23, 2016
    Publication date: November 30, 2017
    Applicant: Giant Manufacturing Co., Ltd.
    Inventors: Wei-Chieh Ho, Chia-Wei Lin, Chao-Shun Yang
  • Patent number: 9818528
    Abstract: A transformer circuit and a manufacturing method thereof are proposed. The transformer circuit includes plural input modules and output modules. Each of the input modules includes a first primary coil and a second primary coil, and each of the primary coils has a first positive input terminal and a negative input terminal. The first primary coil and the second primary coil of each of the input modules are inductively coupled with each other. Each of the output modules includes a secondary coil. Each of the secondary coils includes a first terminal and a second terminal. The first terminal and the second terminal of each of the secondary coils are electrically connected to a first output port and a second output port, respectively. The first primary coil and the second primary coil of each of the input modules are inductively coupled to the secondary coil of the corresponding output module, respectively.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 14, 2017
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Yi-Jan Chen, Hao-Shun Yang
  • Publication number: 20170315415
    Abstract: A transistor substrate is provided. The transistor substrate includes a plurality of data lines and a plurality of scan lines, wherein the scan lines intersects with the data lines to define a plurality of pixel units. One of the pixel units includes a first electrode having a slit substantially parallel to the data lines. The pixel units include a second electrode and a switching transistor. The switching transistor includes a gate electrode connecting to one of the scan lines. The gate electrode has a first edge substantially parallel to the extending direction of the scan lines. The switching transistor includes a drain electrode electrically connected to one of the first electrode and the second electrode. The drain electrode includes an extending portion which extends toward the slit and extends away from an extending line of the first edge. The drain electrode and the slit have an overlapping region.
    Type: Application
    Filed: April 27, 2017
    Publication date: November 2, 2017
    Inventors: Yung-Shun YANG, Chun-Liang LIN, Yi-Ching CHEN, Nai-Fang HSU
  • Publication number: 20170220725
    Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Chin-Shen Lin, Ching-Shun YANG, Hsien YU-TSENG
  • Publication number: 20170176313
    Abstract: The present invention discloses an inspection method for early warning system of industrial security, in which the inspection steps for early warning system comprises: using inspection tool to collect signal characteristics regarding periphery of predetermined area; calculating on collected signal characteristics by means of processor in inspection tool through predetermined programs; determining, based on calculation results, error point of signal characteristics by means of processor in inspection tool; determining the time that abnormal phenomenon is about to occur by means of processor in accordance with data of error point, sending out warning information, and also transmitting collected signal characteristics via wireless transmission unit; and receiving characteristics information transmitted by wireless transmission unit by using wireless transceiver unit and then storing in built-in database for subsequent comparisons.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Chun-Ming YU, Shun-Yang KO
  • Publication number: 20170153468
    Abstract: A LCD device includes a first substrate, a second substrate, a liquid crystal layer and at least one subpixel. The liquid crystal layer and the subpixel are disposed between the first and second substrates. The subpixel includes a first electrode disposed over the first substrate, a first insulation layer disposed over the first electrode, a second electrode disposed over the first insulation layer, a second insulation layer disposed over the second electrode, and a third electrode disposed over the second insulation layer. The rotation of liquid crystal molecules of the liquid crystal layer in the subpixel is controlled by a voltage difference of the first electrode and the third electrode or a voltage difference of the second electrode and the third electrode within a frame time.
    Type: Application
    Filed: November 23, 2016
    Publication date: June 1, 2017
    Inventor: Yung-Shun YANG
  • Patent number: 9665676
    Abstract: An integrated circuit (IC) design system includes a processor; and a non-transitory computer readable medium connected to the processor. The non-transitory computer readable medium is configured to store a configuration file containing a custom IC design parameter, to store a process design kit (PDK) containing a default IC design parameter, and to store instructions for execution by the processor. The instructions for execution by the process include instructions for extracting the custom IC design parameter from the configuration file. The instructions for execution by the process further include instructions for overwriting the default IC design parameter in the PDK with the custom IC design parameter. The instructions for execution by the process further include instructions for creating an IC design file using a module in the PDK using the custom IC design parameter in place of the default IC design parameter.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Shun Yang, Steven Shen, W. R. Lien, Wan-Ru Lin, Chau-Wen Wei
  • Publication number: 20170141003
    Abstract: The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of an integrated chip design using separate temperatures. In some embodiments, the method determines a plurality of actual temperatures that respectively correspond to one or more components within one of a plurality of electrical networks within an integrated chip design. An electromigration margin is determined for a component within a selected electrical network of the plurality of electrical networks. The electromigration margin is determined at one of the plurality of actual temperatures that corresponds to the component within the selected electrical network. The electromigration margin is compared to an electromigration metric to determine if an electromigration violation of the component within the selected electrical network is present.
    Type: Application
    Filed: September 21, 2016
    Publication date: May 18, 2017
    Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
  • Publication number: 20170111946
    Abstract: Disclosed are a method and a system of device-to-device tunnel establishment between small cells, applied to a wireless backhaul management device, a first small cell and a second small cell. The method comprises: matching the first small cell and the second small cell according to a first discovery response and a second discovery response; submitting a match report; replying with a match report response; conducting a D2D connection authentication procedure between the second small cell and the first small cell; wirelessly connecting the second small cell and the first small cell, conducting a connection test and submitting a connection test report; replying with a D2D tunnel establishment decision according to the connection test report; and establishing a D2D tunnel between the second small cell and the first small cell.
    Type: Application
    Filed: October 19, 2016
    Publication date: April 20, 2017
    Inventors: CHUI-CHU CHENG, CHIEH-WEN CHENG, JEN-SHUN YANG, KUEI-LI HUANG, YI-HUAI HSU
  • Publication number: 20160380109
    Abstract: A method for fabricating a transistor including the following steps is provided. First, a gate electrode is formed on a substrate, and a gate insulating layer is formed on the substrate in sequence, wherein the gate insulating layer covers the substrate and the gate electrode. Next, a patterned channel layer and a hard-mask layer are formed on the gate insulating layer, wherein the patterned channel layer and the hard-mask layer are located above the gate electrode, and the hard-mask layer is disposed on the patterned channel layer. Afterwards, a source and a drain are formed on the gate insulating layer by a wet etchant. The part of the hard-mask layer that is not covered by the source and the drain is removed by the wet etchant until the patterned channel layer is exposed, so as to form a plurality of patterned hard-mask layers.
    Type: Application
    Filed: September 13, 2016
    Publication date: December 29, 2016
    Applicant: Au Optronics Corporation
    Inventor: Chao-Shun Yang
  • Publication number: 20160381625
    Abstract: A method for post-authenticating user equipment (UE), a controller and a network system are disclosed. The method includes: determining whether an external channel quality of at least one gateway is higher than a threshold when UE connects to an access point (AP) routed by the gateway; when the external channel quality is not higher than the threshold, authenticating the UE incompletely and controlling the AP to limit a network capability providing to the UE; estimating a future channel capacity of the gateway; calculating a priority weight of each UE; selecting candidate UE from the UEs according to the future channel capacity and the priority weight of each UE; arranging an authenticating mechanism for completely authenticating the candidate UE at a timing point corresponding to the future channel capacity.
    Type: Application
    Filed: December 28, 2015
    Publication date: December 29, 2016
    Inventors: Jyh-Cheng Chen, Jen-Shun Yang, Yi-Hao Lin, Shang-Chun Ou
  • Patent number: 9532304
    Abstract: A method for post-authenticating user equipment (UE), a controller and a network system are disclosed. The method includes: determining whether an external channel quality of at least one gateway is higher than a threshold when UE connects to an access point (AP) routed by the gateway; when the external channel quality is not higher than the threshold, authenticating the UE incompletely and controlling the AP to limit a network capability providing to the UE; estimating a future channel capacity of the gateway; calculating a priority weight of each UE; selecting candidate UE from the UEs according to the future channel capacity and the priority weight of each UE; arranging an authenticating mechanism for completely authenticating the candidate UE at a timing point corresponding to the future channel capacity.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 27, 2016
    Assignees: Industrial Technology Research Institute, National Chiao Tung University
    Inventors: Jyh-Cheng Chen, Jen-Shun Yang, Yi-Hao Lin, Shang-Chun Ou
  • Publication number: 20160373996
    Abstract: The disclosure proposes a routing gateway selecting method, a controller and a vehicles network system. The method is adapted to a controller disposed on a fleet of vehicles configured by a plurality of vehicles, and the controller is configured to select a routing gateway among a plurality of gateways for routing an access point (AP). The routing gateway selecting method includes: predicting a bandwidth of each of the gateways; calculating a transmission cost of each of the gateways based on a load condition and the bandwidth of each of the gateways and a hop count between each of the gateways and the AP; and selecting the routing gateway among the gateways for routing the AP according to the transmission cost of each of the gateways.
    Type: Application
    Filed: October 16, 2015
    Publication date: December 22, 2016
    Inventors: Jen-Shun Yang, Jyh-Cheng Chen, Pei-Chia Hsu, Wei-Chen Sim
  • Patent number: 9521634
    Abstract: A method for operating a machine-to-machine (M2M) device communicating with a gateway includes determining, by the gateway, a timing parameter for synchronizing the machine-to-machine device with the gateway; inserting the timing parameter into a control signal; and transmitting the control signal from the gateway to the machine-to-machine device.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: December 13, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Shubhranshu Singh, Kuei-Li Huang, Jen-Shun Yang, Stephen Gleixner, Ching-Wen Cheng
  • Patent number: D770956
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: November 8, 2016
    Assignee: FORMOSA SAINT JOSE CORP.
    Inventor: Ming-Shun Yang
  • Patent number: D798796
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: October 3, 2017
    Assignee: FORMOSA SAINT JOSE CORPORATION
    Inventor: Ming-Shun Yang