Abstract: The present disclosure provides a display substrate, a fabrication method thereof and a display panel. The display substrate includes a substrate; and a pixel defining layer on the substrate. The display substrate further comprises a display area, a non-display area and a light-transmitting area, the display area and the non-display area at least partially surround the light-transmitting area, the pixel defining layer extends from the display area to the non-display area, the pixel defining layer is provided with a first opening, the first opening comprises a plurality of first sub-openings and a plurality of second sub-openings, the plurality of first sub-openings are in the display area, the plurality of second sub-openings are in the non-display area, and the plurality of second sub-openings are closer to the light-transmitting area than the plurality of first sub-openings.

Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. In the display substrate, the sub-pixel driving circuit includes a driving transistor and a first reset transistor, and a gate electrode of the first reset transistor is electrically connected to the reset signal line pattern, a first electrode of the first reset transistor is electrically connected to the initialization signal line pattern, and a second electrode of the first reset transistor is electrically connected to a gate electrode of the driving transistor; and the shielding pattern is electrically connected to the power signal line pattern, an orthographic projection of the shielding pattern on the substrate overlaps an orthographic projection of the first electrode of the first reset transistor on the substrate.

Abstract: A display substrate, a method for manufacturing the display substrate and a display device are provided. The display substrate includes a display region and a non-display region surrounding the display region. The display substrate further includes: an organic functional layer including a first portion located in the display region and a second portion located in the non-display region. The second portion is provided with at least one isolation groove, and is partitioned into at least two separate sub-portions by the at least one isolation groove, and the at least two sub-portions are arranged sequentially along a first direction from the display region to a boundary of the display substrate.

Abstract: A touch control structure is provided. The touch control structure includes a corner row including a plurality of row mesh blocks electrically connected along a row direction; and a plurality of residual portions in a corner region, and electrically connected to the plurality of row mesh blocks. The touch control structure includes a corner column including a plurality of column mesh blocks electrically connected along a column direction; and a corner column mesh block at least partially in the corner region. The corner column mesh block includes a main portion and a plurality of protrusion portions along an edge of the main portion. The plurality of residual portions and the plurality of protrusion portions are alternately arranged along a direction substantially parallel to the edge of the main portion. The touch control structure further includes a residual connecting conductive plate electrically connecting the plurality of residual portions together.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate, a second conductive layer, a second planarization layer and a plurality of light emitting element groups; each of the plurality of light emitting element groups includes a first light emitting element, a second light emitting element, a third light emitting element and a fourth light emitting element, the fourth light emitting element includes a fourth anode, a plurality of third via holes corresponding to one light emitting element row are approximately located on a first straight line extending along the first direction, and an orthographic projection of the fourth via hole closest to the first straight line on the base substrate is located at a side of the first straight line close to the fourth anode corresponding to the fourth via hole.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate; a plurality of pixel driving circuits; a first conductive layer; a first planarization layer; and a second conductive layer; the second conductive layer includes a first conductive portion, the first conductive portion includes a closed annular portion, which is separated from at least one conductive portion adjacent thereto, each light emitting element groups includes a first light emitting element, the first light emitting element includes a first anode, and an orthographic projection of the first anode overlaps with an orthographic projection of the closed annular portion; the plurality of conductive portions further include a second conductive portion adjacent to the first conductive portion, and an orthographic projection of the second conductive portion on the base substrate overlaps with the orthographic projection of the first anode on the base substrate.

Abstract: A display substrate includes: a base substrate having a display area and a peripheral area surrounding the display area; an electroluminescent device disposed on the base substrate and located in the display area, the electroluminescent device including an anode, an electroluminescent layer, and a cathode disposed in this order on the base substrate; a negative power line disposed on the base substrate and located in the peripheral area, the negative power line extending along a side of the base substrate and being electrically connected to the cathode; and an insulating layer between the base substrate and the negative power line, a side of the insulating layer close to the negative power line being provided with at least a trench. The trench is located in the peripheral area and extends in an extending direction of the negative power line, a part of the negative power line being located in the trench.

Abstract: Disclosed are a display panel and a display device. The display panel includes: at least one group of gate driving signal lines, the gate driving signal lines starting from the driving chip bonding area and going around the display area after passing through the bending area; and at least two first driving voltage lines, the at least two first driving voltage lines respectively starting from the flexible printed circuit bonding area, going through the bending area after passing through two sides of the driving chip bonding area, and extending to be close to the display area, and the at least two first driving voltage lines are respectively at two sides of the at least one group of gate driving signal lines.

Abstract: Disclosed are a display panel and a display device. The display panel includes: a base substrate and a plurality of sub-pixels located on the base substrate; and each sub-pixel includes: a semiconductor layer located on the base substrate and including a first active layer of an initialization transistor, a second active layer of a reset transistor and a third active layer of a data writing transistor; a first conductive layer located on a side of the semiconductor layer and including a data signal line extending in a first direction; and a second conductive layer located on the base substrate and including a drive gate of a drive transistor; and an orthographic projection of the second active layer on the base substrate is located between an orthographic projection of the first active layer on the base substrate and an orthographic projection of the data signal line on the base substrate.

Abstract: A display panel has an opening region, a display region, and first and second peripheral regions; and includes a substrate, a first barrier structure surrounding the display region and in the first peripheral region, a second barrier structure surrounding the opening region and in the second peripheral region, and a crack detection line including first and second portions. The first portion surrounds the opening region, and is on a side of the second barrier structure distal to the display region. Both ends of the second portion are respectively connected to both ends of the first portion. Orthogonal projections of the second portion and the second barrier structure on the substrate overlap each other. The second portion extends into the first peripheral region through the display region. A height of a portion of the second barrier structure overlapping the second portion is less than that of the first barrier structure.

Abstract: Provided is a touch panel. The touch panel includes a back plate and a touch electrode layer disposed on a side of the back plate, wherein the touch electrode layer has a circular touch region and includes a plurality of touch electrodes, the plurality of touch electrodes are distributed in the touch region, and any touch electrode distal from a periphery of the touch region has three side edges sequentially connected end to end.

Abstract: A thin film transistor is provided. The thin film transistor includes a base substrate; a first target layer on the base substrate; a first insulating layer on a side of the first target layer away from the base substrate; an intermediate layer on a side of the first insulating layer away from the first target layer; a second insulating layer on a side of the intermediate layer away from the first insulating layer; and a second target layer on a side of the second insulating layer away from the intermediate layer. The first target layer is electrically connected to the second target layer. The intermediate layer is one of a gate electrode and an active layer, and the first target layer and the second target layer together constitute another one of the gate electrode and the active layer.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, an anode layer and a plurality of pixel driving circuits, the plurality of pixel driving circuits includes a first conductive layer and a second conductive layer; the anode layer includes a first anode, the second conductive layer includes a first conductive portion and a second conductive portion, the second conductive portion includes a main body, a heel block, and a connection block, the heel block is located at a side of the main body close to the first anode, and an orthographic projection of the first conductive portion on the base substrate is overlapped with an orthographic projection of the first anode on the base substrate, and an orthographic projection of the second conductive portion on base substrate is overlapped with an orthographic projection of the first anode on the base substrate.

Abstract: A display motherboard and a manufacturing method of a display substrate are provided. The display motherboard includes: a substrate including a valid area and an edge area, the valid area including a plurality of panel areas and a to-be-cut area, and the panel area including a display area and a frame area; multiple first power lines in each display area and the edge area and extending along a first direction; multiple first display electrodes in each display area and multiple virtual electrodes in the edge area, the first display electrodes and the virtual electrodes being in the same layer; wherein an orthographic projection of each first display electrode on the substrate overlaps an orthographic projection of at most one first power line on the substrate, and an orthographic projection of each virtual electrode on the substrate overlaps orthographic projections of at least two first power lines on the substrate.

Abstract: Provided is a display panel, including a display pixel unit located in a display region, the display pixel unit including a threshold compensation transistor, the threshold compensation transistor including a first channel and a second channel being connected by a conductive connection portion; a dummy pixel unit located in a dummy region; a first signal line located in the dummy region and configured to provide a constant voltage; and a first conductive block connected to the first signal line. The display pixel unit includes a first display pixel unit, the first display pixel unit is a display pixel unit adjacent to the dummy pixel unit in a row direction, and in a plan view of the display panel, the first conductive block at least partially overlaps the conductive connection portion of the threshold compensation transistor of the first display pixel unit. A display device is further provided.

Abstract: A display panel, comprising a first insulating structural layer, a first crack detection line, a second insulating structural layer and a second crack detection line which are sequentially arranged on a substrate, wherein the first crack detection line and the second crack detection line are both located in a peripheral area and are arranged around a display area, one end of the first crack detection line is configured to receive a detection signal, and the other end of the first crack detection line is configured to output a first output signal, and one end of the second crack detection line is configured to receive a detection signal and the other end of the second crack detection line is configured to output a second output signal.

Abstract: An array substrate, a display panel, and a display device are provided. The array substrate includes sub-pixels includes a pixel circuit, and the pixel circuit includes a light emitting element, a storage capacitor, a driving transistor, a data writing transistor, a data line and a first connection structure. The driving transistor is configured to control the light emitting element to emit light; the data line is connected to the first electrode of the data writing transistor and configured to provide a data signal for the data writing transistor; the data writing transistor is configured to write the data signal into the gate electrode of the driving transistor; and the first connection structure is connected to both the gate electrode of the driving transistor and a first electrode plate of the storage capacitor, and the first connection structure and the data line are provided in different layers.

Abstract: A touch structure and a touch display panel are provided. The touch structure includes a first touch; the first touch electrode includes a plurality of first touch electrode portions connected in series, each of the first touch electrode portions includes a first main body portion and a plurality of first finger portions, and the plurality of first finger portions protrude from the first main body portion; at least one first finger portion of at least one of the plurality of first touch electrode portions includes a first finger effective electrode and a first finger dummy electrode, the first finger dummy electrode is insulated from the first finger effective electrode, and the first finger effective electrode is connected with the first main body portion.

Abstract: A display substrate and a display panel are disclosed. The display substrate includes a base substrate having an active area and a peripheral area surrounding the active area; a plurality of sub-pixels, in the active area; a plurality of first pins and a plurality of second pins located in the peripheral area; a plurality of first array test pins located between the plurality of first pins and the plurality of second pins and respectively electrically coupled to a plurality of array test signal lines; and a plurality of second array test pins located between the plurality of first pins and the plurality of second pins and extending in a direction along a boundary of the active area, wherein the plurality of first array test pins are located on at least one side of the plurality of second array test pins in the direction along the boundary of the active area.

Abstract: A coding mode selection method is provided. The method includes acquiring a target frame image of a target video, determining a target coding unit based on the target frame image, the target coding unit comprising a prediction unit, obtaining rate-distortion costs of a symmetric inter prediction mode and a motion merge prediction mode by separately performing estimation on the prediction unit in the symmetric inter prediction mode and the motion merge prediction mode, determining a first candidate prediction mode based on the rate-distortion costs of the symmetric inter prediction mode and the motion merge prediction mode, and determining a second candidate prediction mode set in asymmetric inter prediction modes based on the first candidate prediction mode.